The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 21, 2026

Filed:

Apr. 22, 2022
Applicant:

Adeia Semiconductor Solutions Llc, San Jose, CA (US);

Inventors:

Michael A. Guillorn, Cold Springs, NY (US);

Terence B. Hook, Jericho, VT (US);

Robert R. Robison, Colchester, VT (US);

Reinaldo A. Vega, Mahopac, NY (US);

Rajasekhar Venigalla, Hopewell Junction, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); B82Y 10/00 (2011.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10D 64/66 (2025.01);
U.S. Cl.
CPC ...
H10D 64/018 (2025.01); B82Y 10/00 (2013.01); H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/0323 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6743 (2025.01); H10D 30/6744 (2025.01); H10D 30/6757 (2025.01); H10D 30/751 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 64/01318 (2026.01); H10D 64/01342 (2026.01); H10D 64/017 (2025.01); H10D 64/518 (2025.01); H10D 64/667 (2025.01);
Abstract

A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.


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