The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 30, 2025
Filed:
Mar. 23, 2022
Applicant:
Adeia Semiconductor Solutions Llc, San Jose, CA (US);
Inventors:
John R. Sporre, Albany, NY (US);
Siva Kanakasabapathy, Pleasanton, CA (US);
Andrew M. Greene, Albany, NY (US);
Jeffrey Shearer, Albany, NY (US);
Nicole A. Saulnier, Albany, NY (US);
Assignee:
Adeia Semiconductor Solutions LLC, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/02 (2006.01); H01L 25/065 (2023.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 62/17 (2025.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/0151 (2025.01); H01L 21/02019 (2013.01); H01L 25/0657 (2013.01); H10D 30/024 (2025.01); H10D 30/611 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 62/235 (2025.01); H10D 62/364 (2025.01); H10D 64/017 (2025.01); H10D 84/0135 (2025.01); H10D 84/014 (2025.01); H10D 84/0144 (2025.01); H10D 84/0158 (2025.01); H10D 84/0172 (2025.01); H10D 84/0177 (2025.01); H10D 84/038 (2025.01); H10D 84/834 (2025.01); H10D 84/853 (2025.01);
Abstract
Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.