The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Sep. 14, 2023
Applicant:

Adeia Semiconductor Solutions Llc, San Jose, CA (US);

Inventors:

Daniel C. Edelstein, White Plains, NY (US);

Son V. Nguyen, Schenectady, NY (US);

Takeshi Nogami, Schenectady, NY (US);

Deepika Priyadarshini, Guilderland, NY (US);

Hosadurga Shobha, Niskayuna, NY (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/00 (2026.01); H10P 14/60 (2026.01); H10P 14/692 (2026.01); H10P 70/00 (2026.01); H10W 20/41 (2026.01); H10W 20/42 (2026.01); H10W 20/43 (2026.01);
U.S. Cl.
CPC ...
H10W 20/057 (2026.01); H10P 14/6314 (2026.01); H10P 14/6938 (2026.01); H10P 70/27 (2026.01); H10W 20/033 (2026.01); H10W 20/035 (2026.01); H10W 20/037 (2026.01); H10W 20/038 (2026.01); H10W 20/043 (2026.01); H10W 20/047 (2026.01); H10W 20/048 (2026.01); H10W 20/049 (2026.01); H10W 20/054 (2026.01); H10W 20/062 (2026.01); H10W 20/065 (2026.01); H10W 20/076 (2026.01); H10W 20/077 (2026.01); H10W 20/081 (2026.01); H10W 20/42 (2026.01); H10W 20/425 (2026.01); H10W 20/43 (2026.01);
Abstract

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.


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