International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Adeia Semiconductor Bonding Technologies Inc.

Renesas Electronics America Inc.

Adeia Semiconductor Solutions LLC

Sanjay C Mehta

Tenko Yamashita

Hemanth Jagannathan

Alexander Reznicek

Kangguo Cheng

Chun-chen Yeh

Shogo Mochizuki

Son Van Nguyen

Oleg Gluschenkov

Balasubramanian S Haran

Muthumanickam Sankarapandian

Lars W Liebmann

Balasubramanian Pranatharthiharan

Su Chen Fan

Andre P Labonte

Zuoguang Liu

Stefan Schmitz

Alfred Grill

Hosadurga K Shobha

Thomas J Haigh, Jr

Juntao Li

Xin Miao

Soon-Cheon Seo

Donald Francis Canaperi

Chia-Yu Chen

Thamarai Selvi Devarajan

Bruce Bennett Doris

Junli Wang

Theodorus E Standaert

Chanro Park

Sivananda K Kanakasabapathy

Deepika Priyadarshini

Ruilong Xie

David V Horak

Nicolas J Loubet

Shom Ponoth

Injo Ok

Stephen McConnell Gates

Andrew Mark Greene

Vincent James McGahay

Eric Gerhard Liniger

Vijay Narayanan

Zhenxing Bi

Xiuyu Cai

Qinghuang Lin

Eric R Miller

Veeraraghavan S Basker

Mark Charles Hakey

Ruqiang Bao

Amlan Majumdar

Ravikumar Ramachandran

Marc Adam Bergendahl

Chi-Chun Liu

Robert H Dennard

Thomas M Shaw

Xiao Hu Liu

Christos Dimitrios Dimitrakopoulos

Kevin W Brew

Nicole A Saulnier

Shyng-Tsong Chen

James John Kelly

James J Demarest

Michael Wayne Lane

Charan V Surisetty

Ankit Vora

Ryan O Jung

Lisa F Edge

Chih-Chao Yang

Ali Khakifirooz

Brent A Anderson

Choonghyun Lee

Daniel C Edelstein

Dechao Guo

Judson Robert Holt

Robert Russell Robison

Dominic Joseph Schepis

Andrew Herbert Simon

John Anthony Fitzsimmons

Pranita Kulkarni

Terry Allen Spooner

David Lee Rath

Pierre Morin

Paul Charles Jamison

Wei Lin

Spyridon Skordas

Raghuveer Reddy Patlolla

Huimei Zhou

Stephan Grunow

Raghavasimhan Sreenivasan

William Francis Landers

Kelly Malone

Troy Lawrence Graves-Abe

Timothy Mathew Philip

Charles Robert Davis

Henry Atkinson Nye, Iii

Anita Madan

Jinghong Li

Linus Jang

Iqbal Rashid Saraf

Paul Andrew Ronsheim

A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

Isolation between vertically stacked nanosheet devices

Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Air gap spacer formation for nano-scale semiconductor devices

A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

Phase change memory device

A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

High thermal budget compatible punch through stop integration using doped glass

A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

Gate first technique in vertical transport FET using doped silicon gates with silicide

A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.

Gate tie-down enablement with inner spacer

A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.

Selective contact etch for unmerged epitaxial source/drain regions

A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

Self aligned top extension formation for vertical transistors

A vertical field-effect transistor and a method for fabricating the same. The vertical field-effect transistor includes a substrate and a bottom source/drain region. The vertical field-effect transistor also includes at least one fin structure, and further includes a bottom spacer layer. The bottom spacer layer has a substantially uniform thickness with a thickness variation of less than 3 nm. A gate structure contacts the bottom spacer layer and at least one fin structure. The method includes forming a structure including a substrate, a source/drain region, and one or more fins. A polymer brush spacer is formed in contact with at least sidewalls of the one or more fins. A polymer brush layer is formed in contact with at least the source/drain region and the polymer brush spacer. The polymer brush spacer is removed. Then, the polymer brush layer is reflowed to the sidewalls of the at least one fin.

Vertical field-effect-transistors having a silicon oxide layer with controlled thickness

A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.

Protection of high-K dielectric during reliability anneal on nanosheet structures

Growing community of inventors

Niskayuna, NY, United States of America

Sanjay C Mehta