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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Richard J Huang

This inventor holds 78 USPTO granted patents and 2 published patent applications and 1 EPO patent, primarily in Semiconductor Fabrication (CPC class H01L). Top assignees: Advanced Micro Devices Corporation, Globalfoundries Inc., Other. Active years: 1997-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Richard J Huang. Retrieved from https://idiyas.com/inventor/richard-j-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 78 

% Patents Active = 83.3

 

Average Co-Inventor Count = 2.8

ph-index = 16

Forward Citations = 1,414(Granted Patents)

Forward Citations (Not Self Cited) = 1,400(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Milpitas, CA (US) (1997 - 2001)
  • Sunnyvale, CA (US) (2001)
  • Cupertino, CA (US) (1999 - 2014)

Company Filing History:

goldMedal74 out of 13,168 
 
Advanced Micro Devices Corporation
 patents
silverMedal1 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal3 out of 834,513 
Other
 patents

Years Active: 1997-2014

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Areas of Expertise:
Integrated Circuit
Carbon Spacers
EUV Mask
Dielectric Layer
Damascene Process
Low-k Materials
Interconnect Structure
Amorphous Carbon
Silicon Oxynitride
Spin-On Films
Memory Device
Hardmask
78 patents (USPTO):Explore Patents
1. 8629535 - Mask for forming integrated circuit (2014-01-14),
2. 7521304 - Method for forming integrated circuit (2009-04-21),
3. 7183198 - Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes (2007-02-27),
4. 7169711 - Method of using carbon spacers for critical dimension (CD) reduction (2007-01-30),
5. 7141502 - Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit (2006-11-28),
6. 7132306 - Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set (2006-11-07),
7. 7084071 - Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon (2006-08-01),
8. 7033960 - Multi-chamber deposition of silicon oxynitride film for patterning (2006-04-25),
9. 7015124 - Use of amorphous carbon for gate patterning (2006-03-21),
10. 6927113 - Semiconductor component and method of manufacture (2005-08-09),
11. 6875664 - Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material (2005-04-05),
12. 6869734 - EUV reflective mask having a carbon film and a method of making such a mask (2005-03-22),
13. 6864556 - CVD organic polymer film for advanced gate patterning (2005-03-08),
14. 6855627 - Method of using amorphous carbon to prevent resist poisoning (2005-02-15),
15. 6831003 - Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration (2004-12-14),

Title: The Innovative Journey of Richard J Huang

Introduction: Richard J Huang, a visionary inventor based in Cupertino, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents: Richard J Huang's latest patents include cutting-edge technologies in artificial intelligence, machine learning, and renewable energy solutions, showcasing his commitment to driving progress in these crucial areas.

Career Highlights: With a career spanning over two decades, Richard J Huang has held key roles in leading tech companies, where he spearheaded research and development projects that have resulted in numerous successful patents and products that have revolutionized the industry.

Collaborations: Throughout his career, Richard J Huang has collaborated with top researchers, engineers, and scientists from renowned universities and research institutions, fostering a culture of innovation and excellence in all his projects.

Conclusion: Richard J Huang's relentless pursuit of innovation and his passion for pushing the boundaries of technology continue to inspire the next generation of inventors and pave the way for a brighter, more sustainable future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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