Advanced Micro Devices Corporation

Other

Globalfoundries Inc.

Richard J Huang

Lu You

Robin W Cheung

Dawn M Hopper

Cyrus E Tabery

Simon S Chan

Philip A Fisher

Minh Van Ngo

Guarionex Morales

Scott Allan Bell

Srikanteswara Dakshina-Murthy

Khanh Q Tran

Richard C Nguyen

Angela Tai Hui

Yu Nan Sun

Mark S Chang

Kashmir S Sahota

Fei Wang

Christopher F Lyons

Chi K Chang

Suzette Keefe Pangrle

Lewis N Shen

Pei-Yuan Gao

Paul Raymond Besser

Mark T Ramsbey

Matthew S Buynoski

Calvin T Gabriel

John A Iacoponi

Raymond T Lee

Jacques J Bertrand

Christy M-c Woo

James J Xie

Rajat Rakkhit

John Caffall

Nick Maccrae

Keizaburo Yoshie

Ramkumar Subramanian

Sergey D Lopatin

Steven C Avanzino

Tuan Duc Pham

Ming-Ren Lin

Marina V Plat

Shekhar Pramanick

Pin-Chin Connie Wang

Jean Y Yang

Darrell M Erb

Hartmut Ruelke

Robert A Huertas

Joerg Hohage

Chih Yuh Yang

Marilyn I Wright

David E Brown

Hung-Sheng Chen

John G Pellerin

Jeremy Isaac Martin

David H Matsumoto

Lothar Mergili

Judith Quan Rizzuto

Christof Streck

Seung-Hyun Rhee

Kazutoshi Mochizuki

Kazunori Imaoka

Ibrahim Burki

Kenji Nukui

Toshio Taniguchi

A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Mask for forming integrated circuit

Method for forming integrated circuit

A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.

Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes

A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.

Method of using carbon spacers for critical dimension (CD) reduction

A method for Chemical-Mechanical Polishing utilizes a two step process. The first step utilizes a slurry with abrasive particles which become embedded into a conditioned polishing pad having small cavities in the surface. During the second step the slurry flow is discontinued and the final polishing is performed using the embedded small abrasive particles. Using this method dishing has been reduced considerably, and has enabled the fabrication of a Damascene metal gate NMOSFET fabricated with Atomic Layer Deposition (ALD).

Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit

A method of forming an interlevel dielectric (ILD) layer forms a polymer sacrificial ILD on a substrate. After metallization structures are formed in the polymer sacrificial ILD layer, a low power etch back is performed on the sacrificial ILD layer. Dielectric material is non-conformally deposited as an ILD layer over the substrate and the metallization structures, forming air gaps between some of the metallization structures.

Method of forming an interlevel dielectric layer employing dielectric etch-back process without extra mask set

A method of producing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate and providing an amorphous carbon layer over the polysilicon material layer. The amorphous carbon layer comprises at least one undoped amorphous carbon layer and at least one doped amorphous carbon layer. A portion of the amorphous carbon layer is removed to form a hard mask, and the polysilicon material layer is etched according to the hard mask to form a line of polysilicon material.

Use of multilayer amorphous carbon ARC stack to eliminate line warpage phenomenon

Pinholes in a silicon oxynitride film are reduced by PECVD deposition of a plurality of silicon oxynitride sub-layers in a PECVD apparatus containing multiple chambers. Embodiments include forming a layer of amorphous carbon over a conductive layer, such as doped polycrystalline silicon, on a substrate, transferring the substrate to a multi-chamber PECVD tool and depositing 2 to 7, e.g., 5, sub-layers of dense silicon oxynitride at a total thickness of 300 to 700 &#x212b;.

Multi-chamber deposition of silicon oxynitride film for patterning

A method of producing an integrated circuit includes providing a mask definition structure above a layer of conductive material and providing a mask above the layer of conductive material and in contact with at least a portion of the mask definition structure. The mask definition structure comprises a first material and the mask comprises a second material, wherein at least one of the first and second materials comprises amorphous carbon. The mask definition structure is removed, and the layer of conductive material is patterned according to the mask.

Use of amorphous carbon for gate patterning

A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer. A capping layer is then deposited on both the dielectric portion and the exposed metal interconnect portion of the electrically conductive material.

Semiconductor component and method of manufacture

A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.

Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material

An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of less than 70 nanometers.

EUV reflective mask having a carbon film and a method of making such a mask

A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

CVD organic polymer film for advanced gate patterning

An exemplary embodiment relates to a method of using an amorphous carbon layer to prevent photoresist poisoning. The method includes doping a first amorphous carbon layer located above a substrate, providing an oxide layer above the first amorphous carbon layer where the oxide layer has a pinhole, and providing a second amorphous carbon layer adjacent to the oxide layer. The second amorphous carbon layer is undoped and the second amorphous carbon layer helps prevent photoresist poisoning.

Method of using amorphous carbon to prevent resist poisoning

For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.

Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration

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Cupertino, CA, United States of America

Richard J Huang