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For the Inventor, By the Inventor

Menlo Park, CA, United States of America

Pin-Chin Connie Wang

This inventor holds 52 USPTO granted patents, primarily in Integrated Circuit Interconnects (CPC class H01L). Top assignees: Advanced Micro Devices Corporation, Globalfoundries Inc., Leland Stanford Junior University. Active years: 2001-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pin-Chin Connie Wang. Retrieved from https://idiyas.com/inventor/pin-chin-connie-wang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 52

% Patents Active = 86.5

Average Co-Inventor Count = 2.7

ph-index = 15

Forward Citations = 633(Granted Patents)

Forward Citations (Not Self Cited) = 625(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal50 out of 13,175 
 
Advanced Micro Devices Corporation
 patents
silverMedal1 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal1 out of 5,515 
 
Leland Stanford Junior University
 patents

Years Active: 2001-2010

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Areas of Expertise:
Integrated Circuit
Interconnects
Barrier Layers
Copper Alloys
Electromigration
Chemical Vapor Deposition
Dielectric Layers
Seedless Barriers
Conductor Reservoir
Nucleation Layer
Via Formation
Metal Interfaces
52 patents (USPTO):Explore Patents
1. 7696092 - Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect (2010-04-13),
2. 7169706 - Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition (2007-01-30),
3. 6992004 - Implanted barrier layer to improve line reliability and method of forming same (2006-01-31),
4. 6979903 - Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers (2005-12-27),
5. 6939803 - Method for forming conductor reservoir volume for integrated circuit interconnects (2005-09-06),
6. 6893955 - Manufacturing seedless barrier layers in integrated circuits (2005-05-17),
7. 6861349 - Method of forming an adhesion layer with an element reactive with a barrier layer (2005-03-01),
8. 6841473 - Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap (2005-01-11),
9. 6833625 - Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect (2004-12-21),
10. 6831003 - Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration (2004-12-14),
11. 6815340 - Method of forming an electroless nucleation layer on a via bottom (2004-11-09),
12. 6710452 - Coherent diffusion barriers for integrated circuit interconnects (2004-03-23),
13. 6674170 - Barrier metal oxide interconnect cap in integrated circuits (2004-01-06),
14. 6664185 - Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect (2003-12-16),
15. 6657303 - Integrated circuit with low solubility metal-conductor interconnect cap (2003-12-02),

Title: Innovations and Achievements of Pin-Chin Connie Wang

Introduction

Pin-Chin Connie Wang, based in Menlo Park, CA, is a remarkable inventor with an impressive portfolio of 52 patents. His work primarily focuses on advancing integrated circuit fabrication techniques, highlighting innovative methods that significantly enhance the performance and reliability of electronic components.

Latest Patents

Among his latest innovations is the patent for a "Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect." This method involves fabricating an integrated circuit by forming a barrier layer in a via aperture and utilizing ternary copper alloy as the via material. This unique approach not only reduces the electrical resistance but also promotes an increase in grain size with refined grain boundaries, greatly benefiting the electrical connections within circuits.

Another notable patent is the "Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition." This method illustrates the application of an adhesion precursor in the integrated circuit fabrication process. It includes the introduction of a gas of material over a dielectric substrate, allowing the deposition of a copper layer over an adhesion layer formed by the gas, improving both the adhesion and performance of the resulting circuits.

Career Highlights

Throughout his career, Pin-Chin has contributed to significant advancements in technology while working with prominent organizations. Notably, he has been associated with Advanced Micro Devices Corporation and Leland Stanford Junior University, where he has collaborated on cutting-edge research and development projects.

Collaborations

In his innovative journey, Pin-Chin Wang has worked alongside talented colleagues such as Amit P. Marathe and Sergey D. Lopatin. Their collaborative efforts have propelled the development of new technologies within the semiconductor industry, fostering advancements that are pivotal to modern electronics.

Conclusion

Pin-Chin Connie Wang exemplifies the spirit of innovation through his extensive work in the field of integrated circuits and semiconductor technology. His contributions not only highlight his skills as an inventor but also mark significant milestones in the evolution of electronic devices. Through his relentless pursuit of advancement, he continues to shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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