Advanced Micro Devices Corporation

Globalfoundries Inc.

Leland Stanford Junior University

Pin-Chin Connie Wang

Amit P Marathe

Sergey D Lopatin

Christy Mei-Chu Woo

Paul Raymond Besser

Minh Van Ngo

Steven C Avanzino

Matthew S Buynoski

Lu You

Minh Quoc Tran

Fei Wang

Christy M-c Woo

Jeremias D Romero

Suzette Keefe Pangrle

Joffre F Bernard

Richard J Huang

Darrell M Erb

Kashmir S Sahota

John Espinoza Sanchez, Jr

Diana M Schonauer

Ercan Adem

Theodore H Geballe

Robert H Hammond

Alline F Myers

Khiem B Do

Suzette K Prangrle

A method of fabricating an integrated circuit includes forming a barrier layer along lateral side walls and a bottom of a via aperture and providing a ternary copper alloy via material in the via aperture to form a via. The via aperture is configured to receive the ternary copper alloy via material and electrically connect a first conductive layer and a second conductive layer. The ternary copper alloy via material helps the via to have a lower resistance and an increased grain size with staffed grain boundaries.

Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect

An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition

A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.

Implanted barrier layer to improve line reliability and method of forming same

An integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit. This allows a selective conversion of dielectric materials with no diffusion barrier properties to be converted into good barrier materials which allows larger channels and shrinkage of the integrated circuit.

Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A first dielectric layer on the device dielectric layer has an opening formed therein including a conductor reservoir volume. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A barrier layer lines the second channel and via opening except over the first channel opening. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via. The conductor reservoir volume provides a supply of conductor material to prevent the formation of voids in the first channel and in the via.

Method for forming conductor reservoir volume for integrated circuit interconnects

An integrated circuit manufacturing method is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate and a channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening and a conductor core fills the opening over the barrier layer. A seedless barrier layer lines the opening, and a conductor core fills the opening over the seedless barrier layer. The barrier layer is deposited in the opening and contains atomic layers of barrier material which bonds to the dielectric layer, an intermediate material which bonds to the barrier material layer and to the conductor core, and a conductor core material which bonds to the intermediate material. The conductor core bonds to the conductor core material.

Manufacturing seedless barrier layers in integrated circuits

A method of fabricating an integrated circuit can include forming a barrier material layer along lateral side walls and a bottom of a via aperture which is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer, implanting a first alloy element into an interfacial layer over the barrier material layer, depositing an alloy layer over the interfacial layer. The implanted first alloy element is reactive with the barrier material layer to increase resistance to copper diffusion.

Method of forming an adhesion layer with an element reactive with a barrier layer

A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Manufacturing an integrated circuit with low solubility metal-conductor interconnect cap

For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, the interconnect opening is filled with a conductive fill material comprised of a bulk conductive fill material doped with a first dopant element and a second dopant element that is different from the first dopant element. The dielectric material is comprised of a first dielectric reactant element and a second dielectric reactant element. A diffusion barrier material is formed from a reaction of the first dielectric reactant element and the first dopant element that diffuses from the conductive fill material to the walls to the interconnect opening. In addition, a boundary material is formed from a reaction of the second dielectric reactant element and the second dopant element that diffused from the conductive fill material to the walls of the interconnect opening. The diffusion barrier material and the boundary material form a self-aligned self-aligned skin layer on the walls of the interconnect opening between the conductive fill material and the dielectric material. The self-aligned skin layer prevents diffusion of the conductive fill material into the dielectric material, and the formation of the boundary material prevents diffusion of the second dielectric reactant element into the conductive fill material, such that resistance of the interconnect structure is minimized.

Self-aligned barrier formed with an alloy having at least two dopant elements for minimized resistance of interconnect

For filling an interconnect opening within a porous dielectric material, a diffusion barrier material is deposited onto at least one sidewall of the interconnect opening. A thickness of the diffusion barrier material is equal to or greater than a radius of a pore opened at the sidewall to substantially fill the opened pore. The thickness of the diffusion barrier material is equal to or greater than a mean radius of pores opened at the sidewall to substantially fill a majority of the opened pores. Or, the thickness of the diffusion barrier material is equal to or greater than a radius of a largest pore opened at the sidewall to substantially fill all opened pores. The interconnect opening is then filled with a conductive fill material.

Continuous barrier for interconnect structure formed in porous dielectric material with minimized electromigration

A method of fabricating an integrated circuit can include performing a reactive ion etch (RIE) to form a via aperture in a dielectric layer where the via aperture exposes a portion of a conductive layer located under the dielectric layer, removing polymer residue from the RIE, and forming a nucleation layer over the exposed portion of the conductive layer using an alloy. The nucleation layer can be formed in an electroless process and can improve electromigration reliability, reduce via resistance, eliminate via corrosion, and eliminate copper resputtering on dielectric sidewalls.

Method of forming an electroless nucleation layer on a via bottom

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device and a device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has a channel opening, a barrier layer lining the channel opening, and a conductor core filling the channel opening. The barrier layer has a more negative heat of formation than the channel dielectric layer whereby the barrier layer is reacts with and forms a barrier to diffusion of the material of the conductor core to the channel dielectric layer. The barrier layer also forms a stable compound with the conductor core to form a coherent barrier layer bonding the channel dielectric to the conductor core.

Coherent diffusion barriers for integrated circuit interconnects

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. An interconnect cap is disposed over the conductor core and seed layer and is capped with a capping layer. The interconnect cap is preferably of an indium oxide compound.

Barrier metal oxide interconnect cap in integrated circuits

For fabricating an interconnect structure within a dielectric material comprised of at least one dielectric reactant element, an interconnect opening formed within the dielectric material is filled with a conductive fill material comprised of first and second dopant elements that are different. A diffusion barrier material, that surrounds the conductive fill material, is formed from a reaction of the first dopant element and a dielectric reactant element. Also, a boundary material, that surrounds the conductive fill material, is formed from a reaction of the second dopant element and a dielectric reactant element. The boundary material prevents diffusion of a dielectric reactant element from the dielectric material into the conductive fill material.

An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Growing community of inventors

Menlo Park, CA, United States of America

Pin-Chin Connie Wang