logo

For the Inventor, By the Inventor

Apalachin, NY, United States of America

Patrick Gallagher

USPTO Granted Patents = 15

Average Co-Inventor Count = 3.8

ph-index = 7

Forward Citations = 122(Granted Patents)


Location History:

  • Endicott, NY (US) (2011)
  • Appalachian, NY (US) (2010 - 2013)
  • Apalachin, NY (US) (2010 - 2020)

Company Filing History:

goldMedal15 out of 2,545 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2010-2020

Loading Chart...
15 patents (USPTO):Explore Patents
1. 10706952 - Testing for memories during mission mode self-test (2020-07-07),
2. 10706950 - Testing for memory error correction code logic (2020-07-07),
3. 10551435 - 2D compression-based low power ATPG (2020-02-04),
4. 10541043 - On demand data stream controller for programming and executing operations in an integrated circuit (2020-01-21),
5. 10060976 - Method and apparatus for automatic diagnosis of mis-compares (2018-08-28),
6. 9170301 - Hierarchical compaction for test pattern power generation (2015-10-27),
7. RE44479 - Method and mechanism for implementing electronic designs having power information specifications background (2013-09-02),
8. 8516422 - Method and mechanism for implementing electronic designs having power information specifications background (2013-08-20),
9. 8397113 - Method and system for identifying power defects using test pattern switching activity (2013-03-12),
10. 8271226 - Testing state retention logic in low power systems (2012-09-18),
11. 8001433 - Scan testing architectures for power-shutoff aware systems (2011-08-16),
12. 7979764 - Distributed test compression for integrated circuits (2011-07-12),
13. 7926012 - Design-For-testability planner (2011-04-12),
14. 7779381 - Test generation for low power circuits (2010-08-17),
15. 7739629 - Method and mechanism for implementing electronic designs having power information specifications background (2010-06-15),

Title: Innovations by Patrick Gallagher

Introduction

Patrick Gallagher is an accomplished inventor based in Apalachin, NY (US). He holds a total of 15 patents, showcasing his significant contributions to the field of technology and innovation. His work primarily focuses on improving memory error correction and testing methodologies.

Latest Patents

One of Gallagher's latest patents is related to "Testing for memory error correction code logic." This invention provides systems and methods for enhanced testing of memory error correction code (ECC) logic using memory built-in self-test (MBIST). The embodiment includes a masking element that injects faults into the ECC logic during manufacturing tests and power-on self-tests, allowing for the detection of errors within the ECC logic. Another notable patent is "Testing for memories during mission mode self-test." This invention enables efficient testing of memories during mission mode self-test (MMST) without compromising original functional data. It features a converter that feeds a manipulated version of the original data back into the memories, along with an accumulator to track correctable and uncorrectable errors.

Career Highlights

Patrick Gallagher is currently employed at Cadence Design Systems, Inc., where he continues to innovate and develop cutting-edge technologies. His expertise in memory systems and error correction has made him a valuable asset to the company.

Collaborations

Gallagher has collaborated with notable colleagues such as Vivek Chickermane and Sandeep Bhatia, contributing to various projects and advancements in their field.

Conclusion

Patrick Gallagher's work exemplifies the spirit of innovation in technology, particularly in memory systems and error correction methodologies. His patents reflect a commitment to enhancing the reliability and efficiency of memory technologies.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…