The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 12, 2011
Filed:
Dec. 06, 2007
Nitin Parimi, Endicott, NY (US);
Patrick Gallagher, Endicott, NY (US);
Brian Foutz, Endicott, NY (US);
Vivek Chickermane, Endicott, NY (US);
Nitin Parimi, Endicott, NY (US);
Patrick Gallagher, Endicott, NY (US);
Brian Foutz, Endicott, NY (US);
Vivek Chickermane, Endicott, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method is provided to improve the usability of Design-For-Testability Synthesis (DFTS) tools and to increase the design process productivity. The method comprises receiving a list of testability and design impact analysis functions, to be performed on the circuit, also referred to as a device under test (DUT). The impact analysis leads to the creation of logical transformations, which can be selected by a user with one or more available transformation methods from a list including, but not limited to, boundary scan test logic insertion, scan test logic insertion, memory BIST (built-in-self-test) logic insertion, and logic BIST logic insertion, and scan test data compression insertion logic insertion.