Nitin Parimi

Title: Nitin Parimi: Innovator in Integrated Circuit Design

Introduction

Nitin Parimi is a notable inventor based in San Jose, California. He has made significant contributions to the field of integrated circuit design, particularly in the areas of power management and testability.

Latest Patents

Nitin Parimi holds two patents that showcase his innovative approach. The first patent, titled "2D compression-based low power ATPG," discloses systems and methods for partitioning an integrated circuit into a two-dimensional grid. This design allows for better management of power dissipation during Automatic Test Pattern Generation (ATPG) by enabling and disabling clock gates in specific regions. The second patent, "Design-For-Testability planner," provides a method to enhance the usability of Design-For-Testability Synthesis (DFTS) tools. This method involves performing testability and design impact analysis functions on a device under test, leading to logical transformations that improve the design process productivity.

Career Highlights

Nitin Parimi is currently employed at Cadence Design Systems, Inc., where he continues to develop innovative solutions in integrated circuit design. His work focuses on enhancing the efficiency and effectiveness of testing methodologies in electronic devices.

Collaborations

Nitin collaborates with talented professionals in his field, including Patrick Gallagher and Brian Edward Foutz. Their combined expertise contributes to the advancement of technology in integrated circuit design.

Conclusion

Nitin Parimi is a distinguished inventor whose work in integrated circuit design has led to valuable patents that improve power management and testability. His contributions continue to influence the industry positively.