The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 04, 2020
Filed:
May. 24, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Nitin Parimi, San Jose, CA (US);
Krishna Vijaya Chakravadhanula, Vestal, NY (US);
Patrick Wayne Gallagher, Apalachin, NY (US);
Vivek Chickermane, Slaterville Springs, NY (US);
Brian Edward Foutz, Charlottesville, VA (US);
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
Systems and methods disclosed herein provide for an integrated circuit partitioned into a plurality of regions of a two-dimensional grid, wherein each region of the grid corresponds to similarly located scan flops. The systems and methods also provide for enabling clock gates to scan flops in some regions of the integrated circuit and disabling clock gates to other regions in order to better manage power dissipation during ATPG. Specifically, toggle disabling templates are applied during ATPG in order to enable clock gates in certain regions of the two-dimensional grid.