The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2015
Filed:
Feb. 20, 2013
Cadence Design Systems, Inc., San Jose, CA (US);
Patrick Gallagher, Apalachin, NY (US);
Krishna Chakravadhanula, Vestal, NY (US);
Rajesh Khurana, Noida, IN;
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Abstract
A method and apparatus for hierarchical compaction of test patterns to be applied to an integrated circuit during test is disclosed. The embodiments apply a hierarchical strategy for categorizing test patterns for compaction. A test pattern is considered against a series of criteria for a compacted test pattern. Where all the criteria are met the test pattern is merged into a compacted test pattern. If the criteria are not all met the test patterns are considered against each of the compacted test patterns in turn. This is repeated for each test pattern to create a set of compacted test patterns conforming to the requirements of the criteria. This method and apparatus provides for fine grained control of low power constraints when testing integrated circuits, and includes benefits such as preventing damage during test from burnout and hot spots, and avoiding failures due to IR drop.