The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Jun. 14, 2010
Qi Wang, San Jose, CA (US);
Ankur Gupta, Mountain View, CA (US);
Pinhong Chen, Saratoga, CA (US);
Christina Chu, San Jose, CA (US);
Manish Pandey, San Jose, CA (US);
Huan-chih Tsai, Saratoga, CA (US);
Sandeep Bhatia, San Jose, CA (US);
Yonghao Chen, Groton, MA (US);
Steven Sharp, Lowell, MA (US);
Vivek Chickermane, Ithaca, NY (US);
Patrick Gallagher, Appalachian, NY (US);
Qi Wang, San Jose, CA (US);
Ankur Gupta, Mountain View, CA (US);
Pinhong Chen, Saratoga, CA (US);
Christina Chu, San Jose, CA (US);
Manish Pandey, San Jose, CA (US);
Huan-Chih Tsai, Saratoga, CA (US);
Sandeep Bhatia, San Jose, CA (US);
Yonghao Chen, Groton, MA (US);
Steven Sharp, Lowell, MA (US);
Vivek Chickermane, Ithaca, NY (US);
Patrick Gallagher, Appalachian, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.