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For the Inventor, By the Inventor

San Jose, CA, United States of America

Sandeep Bhatia

USPTO Granted Patents = 12 

Average Co-Inventor Count = 1.9

ph-index = 6

Forward Citations = 92(Granted Patents)


Company Filing History:

goldMedal12 out of 2,542 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2008-2013

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12 patents (USPTO):Explore Patents
1. RE44479 - Method and mechanism for implementing electronic designs having power information specifications background (2013-09-02),
2. 8516422 - Method and mechanism for implementing electronic designs having power information specifications background (2013-08-20),
3. 8078925 - Apparatus for scan testing of integrated circuits with scan registers (2011-12-13),
4. 8001433 - Scan testing architectures for power-shutoff aware systems (2011-08-16),
5. 7925941 - Test compaction using linear-matrix driven scan chains (2011-04-12),
6. 7743298 - Methods and apparatus for scan testing of integrated circuits with scan registers (2010-06-22),
7. 7739629 - Method and mechanism for implementing electronic designs having power information specifications background (2010-06-15),
8. 7693676 - Low power scan test for integrated circuits (2010-04-06),
9. 7657809 - Dual scan chain design method and apparatus (2010-02-02),
10. 7613969 - Method and system for clock skew independent scan register chains (2009-11-03),
11. 7584392 - Test compaction using linear-matrix driven scan chains (2009-09-01),
12. 7457998 - Scan register and methods of using the same (2008-11-25),

Title: Innovator Spotlight: Sandeep Bhatia

Introduction: Sandeep Bhatia, based in San Jose, California, is a distinguished inventor with a focus on electronic design innovations. With a remarkable portfolio of 12 patents, he has significantly contributed to the field of integrated circuit design, enhancing the way power information specifications are implemented.

Latest Patents: Among his latest inventions, Sandeep has developed two pivotal patents that revolutionize electronic design methodologies. The first patent details a method and mechanism for adding power control circuitry at both the RTL and netlist levels. This involves demarcating multiple power domains within a circuit design and specifying various power modes that correspond to different combinations of on/off states for these domains. Additionally, it defines isolation behavior relevant to each power domain, ensuring efficient power management. The second patent outlines a methodology for implementing a unified file format for power-related information in integrated circuits. This invention allows for the provision of power-related design information that is separate from the design files, facilitating better organization and management of power domains and power modes within the circuit design.

Career Highlights: Sandeep Bhatia serves as an invaluable member of Cadence Design Systems, Inc., where he utilizes his expertise in electronic design to drive innovative solutions. His commitment to advancing technology in the industry is evident through his numerous patents and the impact they have on current design practices.

Collaborations: Throughout his career, Sandeep has collaborated with notable colleagues, including Vivek Chickermane and Patrick Gallagher. These partnerships have fostered an environment of creativity and innovation, enabling the development of cutting-edge solutions in electronic design.

Conclusion: Sandeep Bhatia is a leading figure in the realm of electronic design innovations. With his impressive track record of patents and collaborations, he continues to shape the future of power management in integrated circuits. His contributions not only elevate the standards of design practices but also inspire future inventors in the field.

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