The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2011
Filed:
May. 11, 2010
Sandeep Bhatia, San Jose, CA (US);
Oriol Roig, Sunnyvale, CA (US);
Sandeep Bhatia, San Jose, CA (US);
Oriol Roig, Sunnyvale, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
In one embodiment of the invention, an apparatus for scan testing an integrated circuit is provided. The apparatus includes a combinational logic network; and a device for reducing gate switching in the combinational logic network to reduce power consumption during a scan test on the combinational logic network. The device for reducing gate switching in the combinational logic network includes a device for periodically isolating scan data from the combination logic network; and a device for periodically holding functional data coupled into the combinational network substantially steady. In one embodiment of the invention, the device for reducing gate switching in the combinational logic network is a plurality of serially coupled scan registers each having a pair of opposed controlled outputs with one controlled output providing scan output data and another controlled output providing functional data to the combinational logic network.