The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 15, 2010
Filed:
Oct. 30, 2006
Qi Wang, San Jose, CA (US);
Ankur Gupta, Mountain View, CA (US);
Pinhong Chen, Saratoga, CA (US);
Christina Chu, San Jose, CA (US);
Manish Pandey, San Jose, CA (US);
Huan-chih Tsai, Saratoga, CA (US);
Sandeep Bhatia, San Jose, CA (US);
Yonghao Chen, Groton, MA (US);
Steven Sharp, Lowell, MA (US);
Vivek Chickermane, Ithaca, NY (US);
Patrick Gallagher, Appalachian, NY (US);
Qi Wang, San Jose, CA (US);
Ankur Gupta, Mountain View, CA (US);
Pinhong Chen, Saratoga, CA (US);
Christina Chu, San Jose, CA (US);
Manish Pandey, San Jose, CA (US);
Huan-Chih Tsai, Saratoga, CA (US);
Sandeep Bhatia, San Jose, CA (US);
Yonghao Chen, Groton, MA (US);
Steven Sharp, Lowell, MA (US);
Vivek Chickermane, Ithaca, NY (US);
Patrick Gallagher, Appalachian, NY (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.