The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 07, 2020
Filed:
Jun. 19, 2018
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Patrick Gallagher, Apalachin, NY (US);
Steven Lee Gregor, Oswego, NY (US);
Assignee:
CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G11C 29/42 (2006.01); G11C 29/46 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 29/4401 (2013.01); G11C 29/46 (2013.01); G11C 2029/4402 (2013.01);
Abstract
Systems and methods disclosed herein provide for improved testing of memory error correction code ('ECC') logic with memory built-in self-test ('MBIST'). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test ('MFGT') and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.