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For the Inventor, By the Inventor

South Bend, IN, United States of America

Jason M Kulick

This inventor holds 17 USPTO granted patents and 6 published patent applications and 1 EPO patent, primarily in Edge Interconnect Packaging. Top assignees: Indiana Integrated Circuits, LLC, University of Notre Dame Du Lac, Mrsi Systems, LLC. Active years: 2015-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jason M Kulick. Retrieved from https://idiyas.com/inventor/jason-m-kulick

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 17 

% Patents Active = 88.2

 

Average Co-Inventor Count = 2.8

ph-index = 3

Forward Citations = 25(Granted Patents)


Company Filing History:

goldMedal15 out of 16 
 
Indiana Integrated Circuits, LLC
 patents
silverMedal4 out of 388 
 
University of Notre Dame Du Lac
 patents
bronzeMedal2 out of 8 
 
Mrsi Systems, LLC
 patents
4. 2 out of 157 
 
Rochester Institute of Technology
 patents
5. 1 out of 1,493 
 
North Carolina State University
 patents
6. 1 out of 359 
 
Research Triangle Institute
 patents
7. 1 out of 5 
 
Santa Barbara Infrared, Inc
 patents
8. 1 out of 463 
 
Science Applications International Corporation
 patents
where one patent can have more than one assignee

Years Active: 2015-2022

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Areas of Expertise:
Edge Interconnects
Memory Cell Design
Self-Assembly
Circuit Boards
Integrated Circuits
Fiber Array Alignment
Prototyping
Quilt Packaging
Microchip Interconnection
Optical Waveguide
Substrates
Pixel Arrays
17 patents (USPTO):Explore Patents
1. 11523511 - Assembling and handling edge interconnect packaging system (2022-12-06),
2. 11488660 - Adiabatic flip-flop and memory cell design (2022-11-01),
3. 11398463 - Edge interconnect self-assembly substrate (2022-07-26),
4. 11224126 - Edge interconnects for use with circuit boards and integrated circuits (2022-01-11),
5. 10945335 - Assembling and handling edge interconnect packaging system (2021-03-09),
6. 10896898 - Edge interconnect self-assembly substrate (2021-01-19),
7. 10598861 - Method and system to passively align and attach fiber array to laser array or optical waveguide array (2020-03-24),
8. 10410989 - Inter-chip alignment (2019-09-10),
9. 10409004 - Method and system to passively align and attach fiber array to laser array or optical waveguide array (2019-09-10),
10. 10325875 - Edge interconnect packaging of integrated circuits for power systems (2019-06-18),
11. 10182498 - Substrates with interdigitated hinged edge interconnects (2019-01-15),
12. 10056335 - Prototyping of electronic circuits with edge interconnects (2018-08-21),
13. 10050027 - Quilt packaging system with mated metal interconnect nodules and voids (2018-08-14),
14. 9844139 - Method of interconnecting microchips (2017-12-12),
15. 9806030 - Prototyping of electronic circuits with edge interconnects (2017-10-31),

Title: The Innovative Journey of Jason M Kulick

Introduction: Jason M Kulick, a talented inventor hailing from South Bend, IN, has made significant contributions to the world of technology through his groundbreaking innovations.

Latest Patents: Kulick's latest patents showcase his prowess in the field of robotics, with inventions focused on enhancing automation processes in manufacturing industries.

Career Highlights: With a career spanning over two decades, Kulick has established himself as a visionary inventor with a keen eye for identifying gaps in the market and developing solutions to address them. His work has revolutionized the way we approach industrial automation.

Collaborations: Throughout his career, Kulick has collaborated with leading research institutions and universities to further his research and bring his inventions to life. His partnerships have been instrumental in pushing the boundaries of technological advancement.

Conclusion: Jason M Kulick's passion for innovation and dedication to his craft have solidified his position as a prominent figure in the world of inventors. His relentless pursuit of excellence continues to inspire future generations of inventors to push the boundaries of what is possible.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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