Indiana Integrated Circuits, LLC

University of Notre Dame Du Lac

Rochester Institute of Technology

Mrsi Systems, LLC

North Carolina State University

Science Applications International Corporation

Research Triangle Institute

Santa Barbara Infrared, Inc

Jason M Kulick

Tian Lu

Gary H Bernstein

Scott Howard

Douglas C Hall

Anthony Hoffman

Michael Fanto

Stefan Preble

Yi Qian

Jeffrey Steidle

Scott Goodwin

John Philip Timler

Joseph Donald LaVeigne

Alexei Orlov

Robert Joseph Engelhardt, Jr

Douglas C Hopkins

John Lañnon

Gregory Snider

Rene Celis-Cordova

Carlos J Ortega

Joseph Donald Laveigne

A first microchip includes holes or sockets along or in a top face or surface of the first microchip and a second microchip includes nodules extending from a edge of the second microchip. The nodules of the second microchip are received in the holes or sockets along or in the top face or surface of the first microchip, whereupon the first and second microchips are positioned transverse or perpendicular to each other.

Assembling and handling edge interconnect packaging system

In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time Twhereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time Tand/or time Tis/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.

Adiabatic flip-flop and memory cell design

A method of forming a quilt package nodule includes forming a trench in a microchip substrate, forming a metal layer on the bottom, the first and second sides of the trench, and on a top surface of the microchip substrate proximate the first and second sides. forming a mask layer on the metal layer, removing portions of the mask and metal layers on the bottom of the trench, etching the bottom of the trench to increase the depth of the bottom of the trench, removing remaining portions of the mask layer from the metal layer to define the quilt package nodules that protrude beyond edges of the first and second sides, and removing the remaining portion of the trench bottom thereby separating the first and second sides from each other, whereupon each side includes at least one quilt package nodule protruding from the side.

Edge interconnect self-assembly substrate

A substrate assembly includes at least one printed circuit (PC) substrate. Each PC substrate includes a PC top surface and a PC bottom surface spaced from each other and an edge that runs at least partially about a periphery of the PC substrate between the PC top surface and the PC bottom surface. The edge includes or defines on a facet or edge surface of the edge at least one projection that extends transverse or normal to the facet or edge surface. The projection includes a projection top surface and a projection bottom surface spaced from each other and the projection can include or be made of conductive material.

Edge interconnects for use with circuit boards and integrated circuits

Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging&#xae; interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.

A substrate assembly includes a first microchip including a first interconnecting structure and a second microchip including a second interconnecting structure, wherein the first and second interconnecting structures have keyed complementary, interlocking shapes. The first interconnecting structure is interlocked with the second interconnecting structure. Quilt package nodules on edges of the first and second microchips electrically connect circuitry formed on or supported by the first and second microchips.

Disclosed is a method and system for passively aligning optical fibers (), a first waveguide array (), and a second waveguide array () using chip-to-chip vertical evanescent optical waveguides () and (), that can be used with fully automated die bonding equipment. The assembled system () can achieve high optical coupling and high process throughput for needs of high volume manufacturing of photonics, silicon photonics, and other applications that would benefit from aligning optical fibers to lasers efficiently.

Method and system to passively align and attach fiber array to laser array or optical waveguide array

First, second, and third integrated devices each include one or more interconnecting structure. Each interconnecting structure includes (i) one or more interconnecting nodules extending from an edge surface of the device, (ii) one or more interconnect voids formed in an edge surface of the device, or (iii) both (i) and (ii). The one or more interconnecting structures on each of the first and second device is mated with the one or more interconnecting structures on the second device. The first integrated device includes a signal output, the third integrated device includes a signal input; and the second integrated device includes a conductor for conducting a signal from the signal output to the signal input.

Inter-chip alignment

Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.

Edge interconnect packaging of integrated circuits for power systems

A quilt packaging system includes a first microchip substrate having a first edge surface which includes a first conductive interconnecting structure disposed thereon and a second microchip substrate having a first edge surface which includes a second conductive interconnecting structure disposed thereon. The first conductive interconnecting structure is hingedly connected in an interdigitated manner with the second conductive interconnecting structure at an angle that is not a straight angle.

Substrates with interdigitated hinged edge interconnects

In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities are formed in the substrate, a conductive pad is formed in each cavity, and one or more conductive traces are formed on the substrate. Each conductive trace connects a conductive pad to a location, node, or terminal of the electrical circuit. A part of the substrate is removed to form the assembly that includes the electrical circuit, the one or more conductive traces, and a portion of each conductive pad projecting or protruding from the substrate. The electrical circuit can be formed on the substrate, which can be a PCB, or can be formed on a microchip supported by the substrate, which can be formed of semiconductor material, e.g., a semiconductor wafer.

Prototyping of electronic circuits with edge interconnects

First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.

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South Bend, IN, United States of America

Jason M Kulick