The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2019
Filed:
Jul. 17, 2015
Applicant:
Indiana Integrated Circuits, Llc, South Bend, IN (US);
Inventors:
Jason M. Kulick, South Bend, IN (US);
Douglas Hopkins, Cary, NC (US);
Assignees:
North Carolina State University, Raleigh, NC (US);
Indiana Integrated Circuits, LLC, South Bend, IN (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/36 (2006.01); H01L 23/373 (2006.01); H01L 29/06 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 23/3185 (2013.01); H01L 23/36 (2013.01); H01L 23/3735 (2013.01); H01L 23/49838 (2013.01); H01L 24/00 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/065 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 29/0657 (2013.01); H01L 21/563 (2013.01); H01L 2224/05014 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32137 (2013.01); H01L 2224/32147 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73257 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract
Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.