The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 09, 2021

Filed:

Nov. 20, 2017
Applicant:

Indiana Integrated Circuits, Llc, South Bend, IN (US);

Inventors:

Jason M. Kulick, South Bend, IN (US);

Tian Lu, Osceola, IN (US);

Assignee:

Indiana Integrated Circuits, LLC, South Bend, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 1/11 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
H05K 1/18 (2013.01); H05K 1/181 (2013.01); H05K 1/111 (2013.01); H05K 3/34 (2013.01); H05K 2201/1053 (2013.01); Y02P 70/50 (2015.11); Y10T 29/49128 (2015.01);
Abstract

Apparatuses and methods related to the field of microchip assembly and handling, in particular to devices and methods for assembling and handling microchips manufactured with solid edge-to-edge interconnects, such as Quilt Packaging® interconnect technology. Specialized assembly tools are configured to pick up one or more microchips, place the microchips in a specified location aligned to a substrate, package, or another microchip, and facilitate electrical contact through one of a variety of approaches, including solder reflow. This specialized assembly tooling performs heating functions to reflow solder to establish electrical and mechanical interconnections between multiple microchips. Additionally, the interconnected microchips may be arranged in an arbitrarily large array.


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