The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2022
Filed:
Feb. 19, 2021
Indiana Integrated Circuits, Llc, South Bend, IN (US);
University of Notre Dame Du Lac, Notre Dame, IN (US);
Gregory Snider, Niles, MI (US);
Rene Celis-Cordova, South Bend, IN (US);
Alexei Orlov, South Bend, IN (US);
Tian Lu, Osceola, IN (US);
Jason M. Kulick, South Bend, IN (US);
INDIANA INTEGRATED CIRCUITS, LLC, South Bend, IN (US);
UNIVERSITY OF NOTRE DAME DU LAC, Notre Dame, IN (US);
Abstract
In a method computer storage element operation, first and second rising (or falling) clock edges are applied to first and second power inputs of the computer storage element having a transistor array between the first and second power inputs over time Twhereupon a logic value applied to an input of the transistor array is stored therein. Thereafter, first and second falling (or rising) clock edges are applied to the first and second power inputs over time T, whereupon part of an electrical charge or energy associated with the logic value stored in the transistor array is provided to circuitry that generates the first and/or second clock edge(s), wherein the value(s) of time Tand/or time Tis/are greater than a product of RC, where R is resistance associated with the computer storage element, and C is a load capacitance associated with the computer storage element.