Anyang, South Korea

Jai-kwang Shin

This inventor holds 82 USPTO granted patents and 9 published patent applications, primarily in High Electron Mobility Transistors (CPC class H01L29-2003). Top assignees: Samsung Electronics Co., Ltd., Leland Stanford Junior University, Kyungpook National University Industry-Academic Cooperation Foundation. Active years: 2006-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jai-kwang Shin. Retrieved from https://idiyas.com/inventor/jai-kwang-shin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 82 

% Patents Active = 76.8

Average Co-Inventor Count = 4.7

ph-index = 8

Forward Citations = 217(Granted Patents)

Forward Citations (Not Self Cited) = 210(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Anyang, KR (2006 - 2007)
  • Kyungki-do, KR (2008 - 2009)
  • Gyeonggi-do, KR (2009 - 2011)
  • Yongin-si, KR (2010 - 2013)
  • Anyang-si, KR (2006 - 2018)

Company Filing History:


Years Active: 2006-2018

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Areas of Expertise:
High Electron Mobility Transistor
Power Management Chips
Semiconductor Devices
Field Effect Semiconductor
Dual Depletion
Gate Voltage Control
Nitride Semiconductor
Power Switching Device
2-Dimensional Electron Gas
Leakage Current Protection
Image Sensors
Multi-Valued Logic Device
82 patents (USPTO):Explore Patents

Title: Innovations of Jai-Kwang Shin in High Electron Mobility Transistors

Introduction

Jai-Kwang Shin, a prominent inventor based in Anyang-si, South Korea, has made significant contributions to the field of semiconductor technology. With an impressive portfolio of 82 patents, his work primarily focuses on high electron mobility transistors (HEMTs). These innovations have advanced the performance and efficiency of electronic devices.

Latest Patents

Shin's recent patents include groundbreaking designs and fabrication methods of high electron mobility transistors. One notable patent details a HEMT that consists of a source electrode, a gate electrode, a drain electrode, and a channel forming layer where a two-dimensional electron gas (2DEG) is induced. In this design, the source and drain electrodes are located on a channel supplying layer, which has a thickness of less than about 15 nm. This innovation enhances the transistor's performance by optimizing the channel structure.

Another of his latest patents involves high electron mobility transistors exhibiting dual depletion and methods for manufacturing them. This HEMT design features a dual depletion region situated between the source and drain electrodes across a plurality of semiconductor layers with differing polarities. The unique arrangement includes an upper material layer, an intermediate material layer, and a lower material layer, fostering improved functionality in electronic applications.

Career Highlights

Throughout his career, Jai-Kwang Shin has worked with notable organizations. He contributed to advancements in semiconductor technology at Samsung Electronics Co., Ltd., a leader in the global electronics industry. He also spent time at Leland Stanford Junior University, where he furthered research and development in high-performance electronic components.

Collaborations

Shin has collaborated with talented individuals in his field, including coworkers Jae-Joon Oh and Jong-Seob Kim. These partnerships have been instrumental in fostering innovative ideas and advancing research in the rapidly evolving field of semiconductor technology.

Conclusion

Jai-Kwang Shin's inventive prowess has led to significant advancements in the design and manufacturing of high electron mobility transistors. His contributions reflect a deep understanding of semiconductor materials and their applications, positioning him as a key figure in enhancing electronic device performance. As technology continues to evolve, the impact of Shin's innovations will likely resonate throughout the industry for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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