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For the Inventor, By the Inventor

San Jose, CA, United States of America

Jacqueline S Wrench

LinkedIn
USPTO Granted Patents = 30 

Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Location History:

  • San Jose, CA (US) (2020 - 2024)
  • Santa Clara, CA (US) (2021 - 2024)

Company Filing History:

goldMedal30 out of 13,684 
 
Applied Materials, Inc.
 patents

Years Active: 2020-2025

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30 patents (USPTO):
1. 12453086 - Low resistivity metal contact stack (2025-10-21),
2. 12438044 - Methods and apparatus for seam reduction or elimination (2025-10-07),
3. 12328872 - Liner for V-NAND word line stack (2025-06-10),
4. 12230688 - MOSFET gate engineerinng with dipole films (2025-02-18),
5. 12183798 - Threshold voltage modulation for gate-all-around FET architecture (2024-12-31),
6. 12114488 - Enhancing gapfill performance of dram word line (2024-10-08),
7. 12104243 - Methods and apparatus for processing a substrate (2024-10-01),
8. 12100595 - Amorphous silicon-based scavenging and sealing EOT (2024-09-24),
9. 12051734 - PMOS high-k metal gates (2024-07-30),
10. 12022650 - Low resistivity DRAM buried word line stack (2024-06-25),
11. 11997849 - V-NAND stacks with dipole regions (2024-05-28),
12. 11961734 - Treatments to enhance material structures (2024-04-16),
13. 11955332 - Treatments to enhance material structures (2024-04-09),
14. 11908914 - Methods of forming semiconductor structures (2024-02-20),
15. 11894233 - Electronic device having an oxygen free platinum group metal film (2024-02-06),

Title: Jacqueline S Wrench: A Pioneer in Semiconductor Innovations

Introduction

Jacqueline S Wrench, an accomplished inventor based in San Jose, CA, has made significant contributions to the field of semiconductor engineering. With a remarkable portfolio of 24 patents, she is recognized for her innovative solutions that enhance the performance and efficiency of electronic devices.

Latest Patents

Jacqueline’s latest patents include groundbreaking methodologies in MOSFET gate engineering with dipole films and improvements in the gap-fill performance of DRAM word lines. Her MOSFET technology features a metal gate stack involving an interfacial layer and a unique high-κ metal oxide layer with a dipole region formed by niobium (Nb) species. This innovative approach is aimed at improving the functionality and reliability of semiconductor devices. Additionally, her work on memory devices involves the use of a molybdenum silicide nucleation layer, which enhances the performance of memory devices through an intricate process that includes soaking substrates in titanium precursors.

Career Highlights

Jacqueline Wrench is currently employed at Applied Materials, Inc., where she continues to push the boundaries of semiconductor technology. Her extensive work has positioned her as a key figure in the research and development of next-generation memory technologies and components.

Collaborations

Throughout her career, Jacqueline has collaborated with talented professionals such as Yixiong Yang and Srinivas Gandikota. These collaborations have culminated in innovative research efforts that further enhance the efficiency and performance of electronic components in various applications.

Conclusion

Jacqueline S Wrench embodies the spirit of innovation in the semiconductor industry. Through her cutting-edge patents and collaborative efforts, she has paved the way for advancements that are crucial to the electronics sector. Her contributions will undoubtedly continue to influence the development of new technologies for years to come.

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