Applied Materials, Inc.

Jacqueline S Wrench

Yixiong Yang

Srinivas Gandikota

Steven C H Hung

Seshadri Ganguli

Yong Yang

Wei V Tang

Shih Chung Chen

Yongjing Lin

Mandyam Sriram

Naomi Yoshida

Joung Joo Lee

Annamalai Lakshmanan

Karla M Bernal Ramos

Feihu Wang

Luping Li

Sang Ho Yu

Yong Wu

Feng Quan Liu

Paul F Ma

Jeffrey W Anthis

Wen Xiao Chen

Lin Dong

Nobuyuki Sasaki

Jianqiu Guo

Fuqun Grace Vasiknanonte

Mei Yin Chang

David P Thompson

Wei Liu

Robert Jan Visser

Siddarth A Krishnan

Susmit Singha Roy

Lan Yu

Mohith E Verghese

Benjamin Colombeau

Zhebo Chen

Prerna Sonthalia Goradia

Liqi Wu

Geetika Bajaj

Sang-Ho Yu

Jiang Lu

David Michael Thompson

Pradeep Subrahmanyan

Jing Zhou

Sree Rangasai V Kesapragada

Myungsun Kim

Wenyi Liu

Darshan Thakare

Gang Shen

Jose Alexandro Romero

In Seok Hwang

Kunal Bhatnagar

Ria Someshwar

Yumin He

Hsiang Ning Wu

Yuan-hui Lo

ShihChung Chen

Sang-heum Kim

Methods for depositing a metal contact stack on a substrate are described. The metal stack includes a metal cap layer and a molybdenum conductor layer. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity metal contact stack

A method of forming a contact structure in a semiconductor device having a feature includes forming a barrier layer in the feature, wherein the barrier layer is TiN; and forming a metal layer in the feature and over the barrier layer, wherein the metal layer is at least one of aluminum (Al), ruthenium (Ru), or molybdenum (Mo).

Methods and apparatus for seam reduction or elimination

Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an α-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

Liner for V-NAND word line stack

A metal gate stack on a substrate comprises: an interfacial layer on the substrate; a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region comprising niobium (Nb); a high-κ metal oxide capping layer on the high-κ metal oxide layer; a positive metal-oxide-semiconductor (PMOS) work function material above the high-κ metal oxide capping layer; and a gate electrode above the PMOS work function material. The dipole region is formed by driving Nb species of a Nb-based film into the high-κ metal oxide layer to form a dipole region.

MOSFET gate engineerinng with dipole films

A method of forming a gate stack structure includes forming a dipole metal layer on a high-κ gate dielectric layer on a semiconductor structure formed on a substrate, annealing the dipole metal layer, and removing the dipole metal layer. The dipole metal layer comprises dopants in the high-κ gate dielectric layer.

Threshold voltage modulation for gate-all-around FET architecture

Methods of forming memory devices are described. A molybdenum silicide nucleation layer is formed, and the substrate is soaked in a titanium precursor prior to a bulk molybdenum gap fill process. In other embodiments, a molybdenum silicide film is formed in a first process cycle and a second process cycle is performed where the substrate is exposed to a titanium precursor. In further embodiments, a substrate having at least one feature thereon is exposed to a first titanium precursor and a nitrogen-containing reactant. The substrate is then soaked in a second titanium precursor, and then is exposed to a first molybdenum precursor followed by exposure to a silane to form a molybdenum silicide layer on a surface of the substrate.

Enhancing gapfill performance of dram word line

Methods and apparatus for processing a substrate is provided herein. For example, a method for processing a substrate comprises depositing a silicide layer within a feature defined in a layer on a substrate, forming one of a metal liner layer or a metal seed layer atop the silicide layer within the feature via depositing at least one of molybdenum (Mo) or tungsten (W) using physical vapor deposition, and depositing Mo using at least one of chemical vapor deposition or atomic layer deposition atop the at least one of the metal liner layer or the metal seed layer, without vacuum break.

Methods and apparatus for processing a substrate

A sacrificial sealing layer is formed on a high-κ metal gate (HKMG) stack to suppress oxidants, e.g., oxygen and water, from impacting the metal gate stack, thus preserving the device EOT. The method integrated processes that include forming an interfacial layer on the substrate; forming a high-κ metal oxide layer on the interfacial layer, the high-κ metal oxide layer comprising a dipole region adjacent to the interfacial layer, the dipole region; depositing a capping layer on the high-κ metal oxide layer; and forming a sacrificial sealing layer on the capping layer. The dipole region is formed by driving a dopant species, e.g., zinc (Zn), vanadium (V), tungsten (W), molybdenum (Mo), ruthenium (Ru), titanium (Ti), tantalum (Ta), zirconium (Zr), aluminum (Al), niobium (Nb), or mixtures thereof, of a dipole film into the high-κ metal oxide layer to form a dipole region.

Amorphous silicon-based scavenging and sealing EOT

Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiments comprise NbN as a PMOS work function material at a thickness in a range of greater than or equal to 5 Å to less than or equal to 50 Å. The PMOS work function material comprising NbN has an effective work function of greater than or equal to 4.75 eV. Some embodiments comprise HfOas a high-κ metal oxide layer. Some embodiments provide improved PMOS bandedge performance evidenced by improved flatband voltage. Some embodiments exclude transition metal niobium nitride materials as work function materials.

PMOS high-k metal gates

Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.

Low resistivity DRAM buried word line stack

A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.

V-NAND stacks with dipole regions

A method of forming a high-κ dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-κ dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-κ dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-κ dielectric cap layer, and removing the sacrificial silicon cap layer.

Treatments to enhance material structures

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

Methods of forming semiconductor structures

Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.

Electronic device having an oxygen free platinum group metal film

Growing community of inventors

San Jose, CA, United States of America

Jacqueline S Wrench