Koshigaya, Japan

Hideo Miura

This inventor holds 128 USPTO granted patents, primarily in Semiconductor Devices (CPC class H01L2-348). Top assignees: Hitachi, Ltd., Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.. Active years: 1988-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hideo Miura. Retrieved from https://idiyas.com/inventor/hideo-miura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 57.0

Average Co-Inventor Count = 4.6

ph-index = 16

Forward Citations = 1,125(Granted Patents)

Forward Citations (Not Self Cited) = 1,076(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Niihari, JP (1991)
  • Chiyoda, JP (1991)
  • Ibaraki, JP (1988 - 1992)
  • Tsuchiura, JP (1999 - 2009)
  • Tokyo, JP (2003 - 2009)
  • Koshigaya, JP (1995 - 2011)
  • Sendai, JP (2004 - 2014)

Company Filing History:


Years Active: 1988-2014

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Areas of Expertise:
Semiconductor Device
Multi-Chip Module
Field Effect Transistor
Catalyst Structure
Fuel Cell
Conductive Thin Films
Dielectric Properties
Copper Film
Trench
CMOS
Storage Capacitor
Rewiring Layer
128 patents (USPTO):Explore Patents

Title: Hideo Miura: Innovating the Semiconductor Industry

Introduction:

Hideo Miura, hailing from Koshigaya, Japan, is a prolific inventor with a remarkable portfolio of 128 patents. His innovative contributions in the field of semiconductor device manufacturing have had a significant impact on the industry. This article explores Miura's latest patents, career highlights, noteworthy collaborations, and his continuing dedication to pushing the boundaries of innovation.

Latest Patents:

1. Method of manufacturing semiconductor device:

Miura's patented method tackles the issue of resist mask collapse during the plasma process in semiconductor manufacturing. By alternating between two distinct plasma process steps, one incorporating a gas containing fluorine, oxygen, or nitrogen, and the other utilizing a rare gas, Miura enhances the stability of the resist mask, ensuring high-quality device production.

2. Semiconductor device and method for producing the same:

Addressing concerns related to interconnect breakdowns, Miura's invention focuses on achieving a reliable layered interconnect structure without the occurrence of voids. Through careful selection of materials and dimensions, Miura minimizes the diffusion of the conductor film, resulting in improved performance and durability of the semiconductor device.

Career Highlights:

Hideo Miura has made significant contributions to the semiconductor industry during his tenure at several prestigious companies. He has applied his expertise and patented inventions to various aspects of semiconductor device manufacturing. Notably, Miura has worked at Hitachi Co., Ltd, where he contributed to groundbreaking advancements in semiconductor technology. Additionally, his time at Renesas Technology Corp. further solidified his reputation as an outstanding innovator in the field.

Collaborations:

Throughout his career, Hideo Miura has had the privilege of collaborating with talented individuals who share his passion for innovation. Two notable coworkers who have contributed to his successes are Hiroyuki Ohta and Tomio Iwasaki. Their combined expertise and collaborative spirit have undoubtedly left a lasting impact on Miura's pioneering work.

Conclusion:

Hideo Miura's extensive patent portfolio and groundbreaking inventions in the field of semiconductor device manufacturing have solidified his position as an influential figure in the industry. His method for mitigating resist mask collapse during the plasma process and his approach to achieving reliable interconnect structures demonstrate his dedication to addressing critical challenges in semiconductor manufacturing. As Miura continues to push the boundaries of innovation, his visionary contributions will undoubtedly shape the industry's future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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