Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Renesas Electronics Corporation

Hitachi-Kokusai Electric Inc.

Trecenti Technologies, Inc.

Hideo Miura

Hiroyuki Ohta

Tomio Iwasaki

Shuji Ikeda

Asao Nishimura

Takashi Nakajima

Norio Suzuki

Norio Ishitsuka

Hiroya Shimizu

Noriaki Okamoto

Akihiro Yaguchi

Ryuji Kohno

Masatoshi Kanamaru

Shinji Nishihara

Masashi Sahara

Yasuko Yoshida

Hiroshi Moriya

Atsushi Hosogane

Yoshishige Endo

Naoto Ban

Hideki Tanaka

Hideyuki Aoki

Yukihiro Kumagai

Makoto Kitano

Hiroo Masuda

Atsushi Kazama

Tosiho Miyamoto

Masayuki Suzuki

Isamu Asano

Atsuyoshi Koike

Hirohiko Yamamoto

Hisayuki Kato

Akihiko Ariga

Akira Takamatsu

Kazushi Fukuda

Shinichi Horibe

Hirofumi Shimizu

Masamichi Kobayashi

Tatsuya Nagata

Sueo Kawai

Jun Murata

Makoto Ogasawara

Toshio Miyatake

Ryuji Kono

Hiroyuki Uchiyama

Shinji Tanaka

Takashi Hashimoto

Masaharu Kubo

Hiromi Abe

Yoichi Tamaki

Hiromi Shimazu

Shinichi Ishida

Atushi Ogishima

Mitsuo Usami

Nobuyoshi Matsuura

Naotaka Tanaka

Masayuki Kojima

Takeshi Harada

Takahide Ikeda

Kozo Watanabe

Ichio Shimizu

Masatsugu Kametani

Takeshi Kimura

Toshifumi Takeda

Kazushige Sato

Kota Funayama

Kentaro Yamada

Hiroyuki Ota

Yuji Wada

Shinji Sakata

Kenji Kanamitsu

Michimasa Funabashi

Michihiro Mishima

Teruhisa Akashi

Takeshi Terasaki

Munetoshi Zen

Masachika Masuda

Toshiyuki Mine

Gen Murakami

Satoshi Meguro

Masataka Kato

Takahiro Daikoku

Takahiro Naito

Koji Sasaki

Fumio Ootsuka

Naoyuki Kofuji

Akio Yasukawa

Takahiro Onai

Junichi Arita

Kunio Matsumoto

Ikuo Yoshida

Katsuhiko Ichinose

Tasuku Shimizu

Yoshiyuki Kado

Toshiyuki Kikuchi

Takahiro Kumauchi

Shigeo Hattori

Nae Hisano

Masahito Takahashi

Ryozo Yoshino

A problem of a resist mask collapse due to a plasma process is solved. In a method of manufacturing a semiconductor device including steps of a plasma process to a sample having a mask made of an organic material, the plasma process includes a first step of a plasma process under a gas containing any of fluorine, oxygen, or nitrogen, or containing all of them, and a second step of the plasma process under a gas containing a rare gas without containing any of fluorine, oxygen, and nitrogen, and the first step and the second step are repeated.

Method of manufacturing semiconductor device

Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {la&#x2212;al/a}&#xd7;100=A (%) and the difference between the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lb&#x2212;bl/b}&#xd7;100=B (%) satisfy an inequality of {A+B&#xd7;(a/b)}&#x3c;13. In this, the diffusion of the conductor film is retarded.

Semiconductor device and method for producing the same

Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|a&#x2212;a|/a}&#xd7;100=A (%) and the difference between the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|b&#x2212;b|/b}&#xd7;100=B (%) satisfy an inequality of {A+B&#xd7;(a/b)}&#x3c;13. In this, the diffusion of the conductor film is retarded.

Diffusion layers-are formed on a silicon substrate, and gate dielectric filmsand gate lectrodesare formed on these diffusion layers-so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films. Gate dielectric filmsare formed, for example, by CVD. As substrate, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrateor gate electrodes. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

Semiconductor device

In a production of a semiconductor device, after a step in which a thermosetting resin is thermally cured to seal a semiconductor chip with the resin and before a step in which a characteristic of the semiconductor chip is inspected, the thermosetting resin is baked at a temperature higher than the resin sealing temperature in said resin sealing step.

Method for manufacturing semiconductor device

The present invention provides a catalyst structure of high catalytic activity and a fuel cell of high cell output. The catalyst structure comprises a conductive film and catalyst particles formed on the conductive film wherein the difference between lattice constant of a material constituting the conductive film and that of a material constituting the catalyst particles is not more than 16%, and preferably not less than 3%.

Catalyst structure and fuel cell having the same

In forming an electrodeon a silicon oxide filmon a semiconductor substratethrough a silicon oxide film, for example, the gate electrodeis structured in a laminated structure of a plurality of polycrystalline silicon layers. The portion of the gate electrodeis formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

Method of manufacturing semiconductor device having conductive thin films

A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.

Semiconductor device and process for producing the same

A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

Multi-chip module

Diffusion layers-are formed on a silicon substrate, and gate dielectric filmsand gate electrodesare formed on these diffusion layers-so as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films. Gate dielectric filmsare formed, for example, by CVD. As substrate, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrateor gate electrodes. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less thanof the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring

Provided is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|a&#x2212;a|/a}&#xd7;100=A (%) and the difference between the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {|b&#x2212;b|/b}&#xd7;100=B (%) satisfy an inequality of {A+B&#xd7;(a/b)}&#x3c;13. In this, the diffusion of the conductor film is retarded.

Method for producing semiconductor devices that includes forming a copper film in contact with a ruthenium film

The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

Semiconductor device and manufacturing method thereof

There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.

Semiconductor device and method of manufacturing the same

Diffusion layersare formed on a silicon substrate, and gate dielectric filmsand gate electrodesare formed on these diffusion layersso as to be MOS transistors. Zirconium oxide or hafnium oxide is used as a major component of gate dielectric films. Gate dielectric filmsare formed, for example, by CVD. As substrate, there is used one of which the surface is (111) crystal face so as to prevent diffusion of oxygen into silicon substrateor gate electrodes. In case of using a substrate of which the surface is (111) crystal face, diffusion coefficient of oxygen is less than 1/100 of the case in which a silicon substrate of which the surface is (001) crystal face is used, and oxygen diffusion is controlled. Thus, oxygen diffusion is controlled, generation of leakage current is prevented and properties are improved. There is realized a semiconductor device having high reliability and capable of preventing deterioration of characteristics concomitant to miniaturization.

Miniaturized semiconductor device with improved dielectric properties

A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin shallow trench isolation (STI) is formed between adjacent gate electrodes. The drain current characteristics can be improved.

Semiconductor device including active regions and gate electrodes for field effect transistors, with a trench formed between the active regions

Growing community of inventors

Koshigaya, Japan

Hideo Miura