The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2011
Filed:
Apr. 13, 2010
Tomio Iwasaki, Tsukuba, JP;
Hideo Miura, Koshigaya, JP;
Tomio Iwasaki, Tsukuba, JP;
Hideo Miura, Koshigaya, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, a, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {la−al/a}×100=A (%) and the difference between the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, b, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lb−bl/b}×100=B (%) satisfy an inequality of {A+B×(a/b)}<13. In this, the diffusion of the conductor film is retarded.