The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 10, 2007
Filed:
Mar. 18, 2003
Hiroshi Moriya, Chiyoda, JP;
Tomio Iwasaki, Tsukuba, JP;
Hideo Miura, Koshigaya, JP;
Shinji Nishihara, Kokubunji, JP;
Masashi Sahara, Hitachinaka, JP;
Hiroshi Moriya, Chiyoda, JP;
Tomio Iwasaki, Tsukuba, JP;
Hideo Miura, Koshigaya, JP;
Shinji Nishihara, Kokubunji, JP;
Masashi Sahara, Hitachinaka, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
There is provided a semiconductor device having a wiring structure which reduces possibility of a short circuit, and method of making the device. Besides, there is provided a semiconductor device having high reliability. Further, there is provided a semiconductor device having high yield. A wiring line is formed at one main surface side of a semiconductor substrate, and has a laminate structure of an adjacent conductor layer and a main wiring layer. The main wiring layer contains an added element to prevent migration. The adjacent conductor layer is formed of a material for preventing a main constituent element and the added element of the main wiring layer from diffusing into the substrate beneath the adjacent conductor layer, and the concentration of the added element at a location close to an interface between the adjacent conductor layer and the main wiring layer is low compared to the concentration of the added element in the main wiring layer spaced from the adjacent conductor layer.