The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2008
Filed:
Apr. 19, 2005
Norio Ishitsuka, Ibaraki, JP;
Hideo Miura, Koshigaya, JP;
Shuji Ikeda, Koganei, JP;
Norio Suzuki, Mito, JP;
Yasushi Matsuda, Kodaira, JP;
Yasuko Yoshida, Sayama, JP;
Hirohiko Yamamoto, Hachioji, JP;
Masamichi Kobayashi, Kodaira, JP;
Akira Takamatsu, Hamura, JP;
Hirofumi Shimizu, Yamanashi, JP;
Kazushi Fukuda, Ome, JP;
Shinichi Horibe, Akiruno, JP;
Toshio Nozoe, Higashiyamato, JP;
Norio Ishitsuka, Ibaraki, JP;
Hideo Miura, Koshigaya, JP;
Shuji Ikeda, Koganei, JP;
Norio Suzuki, Mito, JP;
Yasushi Matsuda, Kodaira, JP;
Yasuko Yoshida, Sayama, JP;
Hirohiko Yamamoto, Hachioji, JP;
Masamichi Kobayashi, Kodaira, JP;
Akira Takamatsu, Hamura, JP;
Hirofumi Shimizu, Yamanashi, JP;
Kazushi Fukuda, Ome, JP;
Shinichi Horibe, Akiruno, JP;
Toshio Nozoe, Higashiyamato, JP;
Renesas Technology Corp., Tokyo, JP;
Hitachi ULSI Systems Co., Ltd., Tokyo, JP;
Abstract
A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.