This inventor holds 73 USPTO granted patents and 295 published patent applications and 6 EPO patents, primarily in Microelectronics Packaging. Top assignees: Intel Corporation, California Institute of Technology. Active years: 2010-2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:


Years Active: 2010-2026
Areas of Expertise:
Title: Gang Duan: Semiconductor Packaging and Photonic Integration Inventor.
Introduction
Gang Duan is an inventor based in Chandler, Arizona, whose work includes semiconductor packaging and integrated photonic technologies. His portfolio includes 73 patents, reflecting contributions to chip bonding, alignment control, and electro-optical circuit design.
Latest Patents
“Method for Panel-Level Thermo-Compression Bonding” describes a bonding tool with a heated compression head, a stage, a sensor, and a controller. The method uses a recipe-defined displacement and temperature profile alongside measured offsets to control chip gap height and alignment during bonding.
“Electro-Optical Circuits with Modular Switchable Photonic Interface” describes an integrated circuit module combining photonic and electrical ICs with a switchable waveguide device. Controlled by a signal from the electrical IC, the device manages optical signals to or from the photonic IC. The design may use nonlinear optical material and metallization structures, with the ICs hybrid bonded or soldered together and coupled to a system substrate.
Career Highlights
Duan’s listed professional affiliations include Intel Corporation and the California Institute of Technology. His patent work spans advanced bonding processes and modular interfaces for photonic and electrical components.
Collaborations
Duan’s listed coworkers include Srinivas V. Pietambaram and Rahul N. Manepalli. Their names appear among the professional connections associated with his work.
Conclusion
Gang Duan’s patent portfolio highlights innovations in semiconductor assembly and photonic integration, with a focus on precise bonding control and adaptable electro-optical circuit interfaces.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile