The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 29, 2026
Filed:
Sep. 23, 2021
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Suddhasattwa Nad, Chandler, AZ (US);
Gang Duan, Chandler, AZ (US);
Jeremy Ecton, Gilbert, AZ (US);
Brandon Marin, Gilbert, AZ (US);
Ravindranath Mahajan, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 72/20 (2026.01); H10W 72/00 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 72/20 (2026.01); H10W 72/019 (2026.01); H10W 72/072 (2026.01); H10W 72/29 (2026.01); H10W 72/90 (2026.01); H10W 80/011 (2026.01); H10W 72/01253 (2026.01); H10W 72/234 (2026.01); H10W 72/252 (2026.01); H10W 72/923 (2026.01); H10W 72/934 (2026.01); H10W 72/952 (2026.01); H10W 80/033 (2026.01); H10W 90/00 (2026.01); H10W 90/724 (2026.01); H10W 90/794 (2026.01);
Abstract
Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.