The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Dec. 28, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Suddhasattwa Nad, Chandler, AZ (US);

Kristof Darmawikarta, Chandler, AZ (US);

Benjamin Duong, Phoenix, AZ (US);

Gang Duan, Chandler, AZ (US);

Srinivas Pietambaram, Chandler, AZ (US);

Brandon Marin, Gilbert, AZ (US);

Jeremy Ecton, Gilbert, AZ (US);

Jason Steill, Phoenix, AZ (US);

Thomas Sounart, Chandler, AZ (US);

Darko Grujicic, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01G 4/33 (2006.01); H01G 4/012 (2006.01); H01G 4/252 (2006.01); H10W 70/05 (2026.01); H10W 70/63 (2026.01); H10W 90/00 (2026.01); H01G 4/08 (2006.01); H10W 40/22 (2026.01); H10W 72/00 (2026.01);
U.S. Cl.
CPC ...
H01G 4/33 (2013.01); H01G 4/012 (2013.01); H01G 4/252 (2013.01); H10W 70/095 (2026.01); H10W 70/635 (2026.01); H10W 90/00 (2026.01); H01G 4/085 (2013.01); H10W 40/22 (2026.01); H10W 72/877 (2026.01); H10W 90/724 (2026.01); H10W 90/731 (2026.01);
Abstract

Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.


Find Patent Forward Citations

Quick Actions:

Nad, Suddhasattwa. (2026). Package substrate embedded multi-layered in via capacitors (U.S. Patent No. 12784991). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12784991

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