The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Sep. 01, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Brandon C. Marin, Gilbert, AZ (US);

Kristof Kuwawi Darmawikarta, Chandler, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Gang Duan, Chandler, AZ (US);

Benjamin T. Duong, Phoenix, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Jeremy Ecton, Gilbert, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); G11C 5/06 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 62/85 (2025.01); H10D 64/01 (2025.01); H10D 64/64 (2025.01); H10H 20/852 (2025.01); H10H 20/857 (2025.01); H10P 14/20 (2026.01); H10W 20/20 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/90 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 20/20 (2026.01); H10W 70/05 (2026.01); H10W 70/611 (2026.01); H10W 72/20 (2026.01); H10W 74/012 (2026.01); H10W 74/114 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 72/01235 (2026.01); H10W 72/072 (2026.01); H10W 72/07236 (2026.01); H10W 72/073 (2026.01); H10W 72/07338 (2026.01); H10W 72/241 (2026.01); H10W 72/877 (2026.01); H10W 72/942 (2026.01); H10W 72/944 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

Embodiments of a microelectronic assembly comprise: a package substrate including a first integrated circuit (IC) die embedded therein; and a second IC die coupled to the package substrate and conductively coupled to the first IC die by vias in the package substrate. The package substrate has a first side and an opposing second side, the second IC die is coupled to the first side of the package substrate, the first IC die is between the first side of the package substrate and the second side of the package substrate, the package substrate comprises a plurality of layers of conductive traces in an organic dielectric material, the first IC die is surrounded by the organic dielectric material of the package substrate, the vias are in the organic dielectric material between the first IC die and the first side of the package substrate, and the first IC die comprises through-substrate vias.


Find Patent Forward Citations

Marin, Brandon. (2026). Package substrate with embedded dies in buildup layers (U.S. Patent No. 12772879). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772879

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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