The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jun. 24, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Brandon C. Marin, Gilbert, AZ (US);

Suddhasattwa Nad, Chandler, AZ (US);

Srinivas V. Pietambaram, Chandler, AZ (US);

Gang Duan, Chandler, AZ (US);

Jeremy D. Ecton, Gilbert, AZ (US);

Kristof Darmawikarta, Chandler, AZ (US);

Sameer Paital, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/69 (2026.01); H10P 14/694 (2026.01); H10W 70/05 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/69 (2026.01); H10P 14/69433 (2026.01); H10W 70/095 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/701 (2026.01); H10W 90/724 (2026.01);
Abstract

Embodiments herein relate to systems, apparatuses, or processes directed to forming an LGA pad on a side of a substrate, with a layer of silicon nitride between the LGA pad and a dielectric layer of the substrate. The LGA pad may have a reduced footprint, or a reduced lateral dimension with respect to a plane of the substrate, as compared to legacy LGA pads to reduce insertion loss by reducing the resulting capacitance between the reduced LGA footprint and metal routings within the substrate. The layer of silicon nitride may provide additional mechanical support for the reduced footprint. Other embodiments may be described and/or claimed.


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