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Singapore, Singapore

Chung Woh Lai

This inventor holds 24 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Fabrication. Top assignees: Chartered Semiconductor Manufacturing Ltd (Corporation), Globalfoundries Singapore Pte. Ltd., International Business Machines Corporation. Active years: 2002-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Chung Woh Lai. Retrieved from https://idiyas.com/inventor/chung-woh-lai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 24 (Patent Applications = 3)

% Patents Active = 45.8

Average Co-Inventor Count = 6.9

ph-index = 5

Forward Citations = 88(Granted Patents)

Company Filing History:

Chartered Semiconductor Manufacturing Ltd (Corporation)

Globalfoundries Singapore Pte. Ltd.

8 out of 166,425

International Business Machines Corporation

4. 3 out of 132,108

Samsung Electronics Co., Ltd.

5. 2 out of 15,040

Infineon Technologies Ag

6. 2 out of 244

Infineon Technologies North America Corp.

where one patent can have more than one assignee

Years Active: 2002-2014

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Areas of Expertise:

Dislocation Engineering

Memory Device

Integrated Circuits

SiGe

MOSFET

Epitaxial Growth

Low-K Dielectric

Thermal Stability

Transistor Structures

Salicidation

Stress Optimization

Trench Isolation

24 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8865572 - Dislocation engineering using a scanned laser (2014-10-21),

2. 8865571 - Dislocation engineering using a scanned laser (2014-10-21),

3. 8716081 - Capacitor top plate over source/drain to form a 1T memory device (2014-05-06),

4. 8624329 - Spacer-less low-K dielectric processes (2014-01-07),

5. 8274115 - Hybrid orientation substrate with stress layer (2012-09-25),

6. 8198194 - Methods of forming p-channel field effect transistors having SiGe source/drain regions (2012-06-12),

7. 8178417 - Method of forming shallow trench isolation structures for integrated circuits (2012-05-15),

8. 8143651 - Nested and isolated transistors with reduced impedance difference (2012-03-27),

9. 8138066 - Dislocation engineering using a scanned laser (2012-03-20),

10. 8053327 - Method of manufacture of an integrated circuit system with self-aligned isolation structures (2011-11-08),

11. 7999325 - Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS (2011-08-16),

12. 7999300 - Memory cell structure and method for fabrication thereof (2011-08-16),

13. 7977185 - Method and apparatus for post silicide spacer removal (2011-07-12),

14. 7955936 - Semiconductor fabrication process including an SiGe rework method (2011-06-07),

15. 7935593 - Stress optimization in dual embedded epitaxially grown semiconductor processing (2011-05-03),