Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Infineon Technologies North America Corp.

Chung Woh Lai

Yong Meng Lee

Zhao Lun

Johnny Widodo

Shailendra Mishra

Liang Choo Hsia

Wenhe Lin

Young Way Teh

Shyue Seng Tan

John Leonard Sudijono

Khee Yong Lim

Lee Wee Teo

Hui Peng Koh

Jeffrey Chee

Wee Leng Tan

Huang Liu

Henry K Utomo

Jin-Ping Han

James Yong Meng Lee

Xiao Hu Liu

Anita Madan

J Campbell Scott

Wen Zhi Gao

Jong Ho Yang

Klaus W Schwarz

Shiang Yang Ong

Eng Hua Lim

Fang Chen

Arthur Ang

Yew Tuck Chow

Judson Robert Holt

Kern Rim

Mei Sheng Zhou

Brian Joseph Greene

Thomas W Dyer

Siddhartha Panda

Bei Chao Zhang

Eric C Harley

Liang-Choo Hsia

Charles Lin

Alex K H See

Richard J Murphy

Richard O Henry

Peter Chew

Beichao Zhang

Hyung-rae Lee

James Yongmeng Lee

Wenzhi Gao

Yong Siang Tan

Hai Jiang Peng

A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.

Dislocation engineering using a scanned laser

A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.

A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.

Capacitor top plate over source/drain to form a 1T memory device

A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Spacer-less low-K dielectric processes

A hybrid orientation substrate includes a base substrate having a first orientation, a first surface layer having a first orientation disposed on the base substrate in a first region, and a second surface layer disposed on the base substrate in a second region. The second surface layer has an upper sub-layer having a second orientation, and a lower sub-layer between the base substrate and the upper sub-layer. The lower sub-layer having a first stress induces a second stress on the upper sub-layer.

Hybrid orientation substrate with stress layer

Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.

Methods of forming p-channel field effect transistors having SiGe source/drain regions

A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.

Method of forming shallow trench isolation structures for integrated circuits

A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rof transistors in iso and nested regions can be matched.

Nested and isolated transistors with reduced impedance difference

A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.

An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.

Method of manufacture of an integrated circuit system with self-aligned isolation structures

A memory cell includes a substrate, an access transistor and a storage capacitor. The access transistor comprising a gate stack disposed on the substrate, and a first and second diffusion region located on a first and second opposing sides of the gate stack. The storage capacitor comprises a first capacitor plate comprising a portion embedded within the substrate below the first diffusion region, a second capacitor plate and a capacitor dielectric sandwiched between the embedded portion of the first capacitor plate. At least a portion of the first diffusion region forms the second capacitor plate.

Memory cell structure and method for fabrication thereof

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Method and apparatus for post silicide spacer removal

A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25&#xb0; C. to about 65&#xb0; C.

Semiconductor fabrication process including an SiGe rework method

Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo implantation masks for both horizontal and vertical PC

Stress optimization in dual embedded epitaxially grown semiconductor processing

Growing community of inventors

Singapore, Singapore

Chung Woh Lai