The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2011
Filed:
Sep. 30, 2008
Young Way Teh, Singapore, SG;
Yong Meng Lee, Singapore, SG;
Chung Woh Lai, Singapore, SG;
Wenhe Lin, Singapore, SG;
Khee Yong Lim, Singapore, SG;
Wee Leng Tan, Singapore, SG;
John Sudijono, Singapore, SG;
Hui Peng Koh, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
Young Way Teh, Singapore, SG;
Yong Meng Lee, Singapore, SG;
Chung Woh Lai, Singapore, SG;
Wenhe Lin, Singapore, SG;
Khee Yong Lim, Singapore, SG;
Wee Leng Tan, Singapore, SG;
John Sudijono, Singapore, SG;
Hui Peng Koh, Singapore, SG;
Liang Choo Hsia, Singapore, SG;
Globalfoundries Singapore Pte. Ltd., Singapore, SG;
Abstract
An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.