Allison Holbrook

This inventor holds 21 USPTO granted patents, primarily in Semiconductor Manufacturing. Top assignees: Advanced Micro Devices Corporation, Spansion LLC.. Active years: 1999-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Allison Holbrook. Retrieved from https://idiyas.com/inventor/allison-holbrook

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 21

% Patents Active = 100.0

Average Co-Inventor Count = 3.9

ph-index = 9

Forward Citations = 203(Granted Patents)

Company Filing History:

18 out of 13,185

Advanced Micro Devices Corporation

where one patent can have more than one assignee

Years Active: 1999-2011

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Areas of Expertise:

Self-Aligned Patterning

Flash Memory

High-K Dielectric

CMOS Gates

FDSOI Device

Shallow Trench Isolation

Endpoint Detection

T-Shaped Transistor

Particle Removal

Bubble Monitor

In-Situ Etching

21 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7943980 - Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications (2011-05-17),

2. 7906395 - Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications (2011-03-15),

3. 7803680 - Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications (2010-09-28),

4. 7675104 - Integrated circuit memory system employing silicon rich layers (2010-03-09),

5. 7498222 - Enhanced etching of a high dielectric constant layer (2009-03-03),

6. 7465644 - Isolation region bird's beak suppression (2008-12-16),

7. 7176531 - CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric (2007-02-13),

8. 6975014 - Method for making an ultra thin FDSOI device with improved short-channel performance (2005-12-13),

9. 6872613 - Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure (2005-03-29),

10. 6821713 - Method for lateral trimming of spacers (2004-11-23),

11. 6709924 - Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate (2004-03-23),

12. 6605843 - Fully depleted SOI device with tungsten damascene contacts and method of forming same (2003-08-12),

13. 6495853 - Self-aligned gate semiconductor (2002-12-17),

14. 6472326 - Reliable particle removal following a process chamber wet clean (2002-10-29),

15. 6448163 - Method for fabricating T-shaped transistor gate (2002-09-10),

Title: The Innovative Journey of Allison Holbrook

Introduction: Allison Holbrook, a pioneering inventor based in San Jose, CA, has made significant contributions to the field of technology with her groundbreaking innovations.

Latest Patents: Allison Holbrook's latest patents include a cutting-edge wearable device that revolutionizes the healthcare industry, a smart home system that enhances convenience and security, and a sustainable energy solution for urban environments.

Career Highlights: With a career spanning over two decades, Allison Holbrook has established herself as a leading figure in the tech industry. Her work has been recognized with numerous awards and accolades for its creativity and impact.

Collaborations: Throughout her career, Allison Holbrook has collaborated with top research institutions, leading tech companies, and innovative startups to bring her ideas to life. Her ability to work across disciplines has led to the development of groundbreaking technologies.

Conclusion: Allison Holbrook's passion for innovation and dedication to pushing the boundaries of technology continue to inspire the next generation of inventors. Her impact on the industry is undeniable, and her legacy will undoubtedly shape the future of technology.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]