The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2007
Filed:
Dec. 22, 2004
Qi Xiang, San Jose, CA (US);
Huicai Zhong, Wappinger Falls, NY (US);
Jung-suk Goo, Stanford, CA (US);
Allison K. Holbrook, San Jose, CA (US);
Joong S. Jeon, Cupertino, CA (US);
George J. Kluth, Campbell, CA (US);
Qi Xiang, San Jose, CA (US);
Huicai Zhong, Wappinger Falls, NY (US);
Jung-Suk Goo, Stanford, CA (US);
Allison K. Holbrook, San Jose, CA (US);
Joong S. Jeon, Cupertino, CA (US);
George J. Kluth, Campbell, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.