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For the Inventor, By the Inventor

Stanford, CA, United States of America

Jung-Suk Goo

This inventor holds 32 USPTO granted patents and 1 published patent application and 1 EPO patent, primarily in Strained Silicon Technology. Top assignees: Advanced Micro Devices Corporation, Globalfoundries Inc., Advanced Micro Device, Inc.. Active years: 2004-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jung-Suk Goo. Retrieved from https://idiyas.com/inventor/jung-suk-goo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 32 

% Patents Active = 75.0


Average Co-Inventor Count = 3.4

ph-index = 12

Forward Citations = 787(Granted Patents)


Location History:

  • Stanford, CA (US) (2004 - 2011)
  • Los Altos, CA (US) (2010 - 2014)

Company Filing History:

goldMedal24 out of 13,168 
 
Advanced Micro Devices Corporation
 patents
silverMedal8 out of 5,671 
 
Globalfoundries Inc.
 patents
bronzeMedal1 out of 24 
 
Advanced Micro Device, Inc.
 patents
where one patent can have more than one assignee

Years Active: 2004-2014

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Areas of Expertise:
Strained Silicon
MOSFET
DRAM Cells
Integrated Circuit
Transistor Modeling
FinFET
Body Effect Measurement
Thermal Conductivity
Silicon-on-Insulator
Aging Simulations
Shallow Trench Isolation
Carrier Mobility
32 patents (USPTO):Explore Patents
1. 8818785 - Method and apparatus for simulating gate capacitance of a tucked transistor device (2014-08-26),
2. 8618592 - Dynamic random access memory (DRAM) cells and methods for fabricating the same (2013-12-31),
3. 8586981 - Silicon-on-insulator ('SOI') transistor test structure for measuring body-effect (2013-11-19),
4. 8293606 - Body tie test structure for accurate body effect measurement (2012-10-23),
5. 8275596 - Method for robust statistical semiconductor device modeling (2012-09-25),
6. 8099269 - Two-step simulation methodology for aging simulations (2012-01-17),
7. 7977172 - Dynamic random access memory (DRAM) cells and methods for fabricating the same (2011-07-12),
8. 7932103 - Integrated circuit system with MOS device (2011-04-26),
9. 7923785 - Field effect transistor having increased carrier mobility (2011-04-12),
10. 7880229 - Body tie test structure for accurate body effect measurement (2011-02-01),
11. 7761823 - Method for adjusting a transistor model for increased circuit simulation accuracy (2010-07-20),
12. 7732336 - Shallow trench isolation process and structure with minimized strained silicon consumption (2010-06-08),
13. 7462549 - Shallow trench isolation process and structure with minimized strained silicon consumption (2008-12-09),
14. 7176531 - CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric (2007-02-13),
15. 7170084 - Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication (2007-01-30),

Title: Jung-Suk Goo: Pioneering Inventor from Stanford

Introduction: Jung-Suk Goo is a highly accomplished inventor based in Stanford, CA, known for her groundbreaking contributions to various fields.

Latest Patents: Jung-Suk Goo's latest patents include innovative technologies in the fields of biotechnology, artificial intelligence, and renewable energy.

Career Highlights: With a career spanning over two decades, Jung-Suk Goo has established herself as a leading figure in the innovation landscape, with numerous patents to her name and a reputation for pushing the boundaries of what is possible.

Collaborations: Throughout her career, Jung-Suk Goo has collaborated with top research institutions, leading companies, and talented individuals to bring her inventions to life and make a lasting impact on society.

Conclusion: Jung-Suk Goo's dedication to innovation and her relentless pursuit of excellence continue to inspire the next generation of inventors and shape the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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