The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2014
Filed:
Nov. 03, 2011
Jung-suk Goo, Los Altos, CA (US);
Ciby Thuruthiyil, Fremont, CA (US);
Venkat Ramasubramanian, Sunnyvale, CA (US);
John Faricelli, Stow, MA (US);
Jung-Suk Goo, Los Altos, CA (US);
Ciby Thuruthiyil, Fremont, CA (US);
Venkat Ramasubramanian, Sunnyvale, CA (US);
John Faricelli, Stow, MA (US);
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at least a portion of the floating gate electrode is provided. The method includes receiving a first netlist having an entry for the tucked transistor device in a computing apparatus. The entry defines parameters associated with the gate electrode and the diffusion region. A parasitic capacitance component is added to the entry representing a gate capacitance between the floating gate and the diffusion region in the computing apparatus.