Stow, MA, United States of America

John Vincent Faricelli

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignees: Advanced Micro Devices Corporation, Ati Technologies Ulc, Globalfoundries Inc.. Active years: 2014-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John Vincent Faricelli. Retrieved from https://idiyas.com/inventor/john-vincent-faricelli

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 2 

% Patents Active = 50.0

Average Co-Inventor Count = 4.8

ph-index = 2

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2014-2018

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2 patents (USPTO):Explore Patents

Title: **Inventor Spotlight: John Vincent Faricelli**

Introduction

John Vincent Faricelli is a noteworthy inventor based in Stow, MA, with a significant contribution to the field of semiconductor technology, holding two patents to his name. His innovative work focuses on enhancing the efficiency and reliability of semiconductor devices, reflecting his expertise and commitment to advancing technology.

Latest Patents

Faricelli's latest patents showcase his ingenuity in semiconductor operations. His first patent, titled "Dynamic Reliability Quality Monitoring," introduces a system and method for managing operating modes within a semiconductor chip. This invention aims to optimally balance power and performance while adhering to reliability targets. The semiconductor chip features a functional unit alongside a corresponding reliability monitor that tracks actual usage values, compares them to expected usage based on the chip's age, and adjusts operational parameters accordingly.

The second patent, "Method and Apparatus for Simulating Gate Capacitance of a Tucked Transistor Device," provides a novel approach to simulating tucked transistor devices. This method incorporates a diffusion region defined in a semiconductor layer and involves complex interactions between gate electrodes and parasitic capacitance. Faricelli’s approach includes receiving specific parameters within a computing apparatus to accurately represent the gate capacitance, thereby enhancing simulation accuracy.

Career Highlights

Throughout his career, John Vincent Faricelli has made a significant impact in the technology sector, having worked with prominent companies such as Advanced Micro Devices Corporation and ATI Technologies ULC. His work at these companies has positioned him at the forefront of advancements in semiconductor design and development.

Collaborations

Faricelli has collaborated with notable coworkers such as Stephen Victor Kosonocky and Thomas Burd. These collaborations have contributed to his successful project completions and advancements in semiconductor technologies, showcasing the power of teamwork in driving innovation.

Conclusion

John Vincent Faricelli's contributions to the field of semiconductor technology through his patents and professional experiences highlight his role as an influential inventor. His ongoing commitment to improving the reliability and performance of semiconductor devices continues to pave the way for future innovations in this critical area of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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