The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2010
Filed:
Jul. 31, 2006
Amol Ramesh Joshi, Sunnyvale, CA (US);
Harpreet Sachar, San Jose, CA (US);
Youseok Suh, Cupertino, CA (US);
Shenqing Fang, Fremont, CA (US);
Chih-yuh Yang, San Jose, CA (US);
Lovejeet Singh, Sunnyvale, CA (US);
David H. Matsumoto, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Kuo-tung Chang, Saratoga, CA (US);
Scott A. Bell, San Jose, CA (US);
Allison Holbrook, San Jose, CA (US);
Satoshi Torii, Mie, JP;
Amol Ramesh Joshi, Sunnyvale, CA (US);
Harpreet Sachar, San Jose, CA (US);
YouSeok Suh, Cupertino, CA (US);
Shenqing Fang, Fremont, CA (US);
Chih-Yuh Yang, San Jose, CA (US);
Lovejeet Singh, Sunnyvale, CA (US);
David H. Matsumoto, San Jose, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Kuo-Tung Chang, Saratoga, CA (US);
Scott A. Bell, San Jose, CA (US);
Allison Holbrook, San Jose, CA (US);
Satoshi Torii, Mie, JP;
Spansion LLC, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.