Advanced Micro Devices Corporation

Spansion LLC.

Allison Holbrook

Sunny Cherian

Jiahua Huang

Kuo-Tung Chang

Youseok Suh

Fei Wang

Zoran Krivokapic

Scott Allan Bell

Shenqing Fang

Tim Thurgate

Qi Xiang

Jeffrey Allan Shields

Huicai Zhong

William George En

Simon S Chan

George Jonathan Kluth

Joong Jeon

Jung-Suk Goo

Phillip Lawrence Jones

James K Kai

Hidehiko Shiraiwa

Allen S Yu

Chih-Yuh Yang

Kai Yang

Amol Ramesh Joshi

Satoshi Torii

Harpreet Kaur Sachar

Weidong Qian

John C Foster

David H Matsumoto

Lovejeet Singh

Theodros W Mariam

James Chiang

Shenging Fang

Aaron A Fernandes

Omar Serna

Darlene Smith

Greg A Johnson

A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductur applications

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Integrated circuit memory system employing silicon rich layers

A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.

Enhanced etching of a high dielectric constant layer

A structure for electrically isolating semiconductor devices includes a semiconducting layer and a layer of aluminum oxide formed in a pattern over the semiconducting layer, where the pattern exposes a portion of the semiconducting layer. The structure further includes an electrical isolation region formed in the exposed portion of the semiconducting layer, where the isolation region does not substantially encroach a region beneath the layer of aluminum oxide.

Isolation region bird's beak suppression

According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.

CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric

A method for forming a FDSOI device with channel length less than 50 nm with good short channel control. The gate has a tapered polysilicon spacer and a dielectric spacer. A polysilicon gate feature is formed and dielectric sidewall spacers are formed thereon. The polysilicon gate feature is then etched to form tapered poly features separated by a gap. A gate dielectric is deposited at low temperature, then metal is deposited into the gap to form the metal gate.

Method for making an ultra thin FDSOI device with improved short-channel performance

Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure

Spacer etch trim techniques are provided. The method controllably trims a multi-film stack spacer utilizing a self-limiting etch technique. The method may use a dry etch etcher with low bias power. The dry etch process may also use other modified parameters, such as gas flows and various pressures.

Method for lateral trimming of spacers

For fabricating a shallow trench isolation structure, a notched masking structure is formed over an active area of a semiconductor substrate. A shallow trench opening is formed at a side of the active area with a top corner of the shallow trench opening being exposed and facing a notched surface of the notched masking structure. Liner oxide is formed in a thermal oxidation process at the top corner of the shallow trench opening to round the top corner of the shallow trench opening. The liner oxide may also be formed on walls including the bottom corner of the shallow trench opening during the thermal oxidation process. The shallow trench opening is then filled with a trench dielectric material to form the shallow trench isolation structure.

Fabrication of shallow trench isolation structures with rounded corner and self-aligned gate

A fully depleted field effect transistor formed in a silicon on insulator (SOI) substrate includes a body region formed in a silicon device layer over an isolation layer of the SOI substrate. A gate is positioned above the body region and includes a base gate region adjacent the body region and a wide top gate region formed of tungsten damascene and spaced apart from the body region. An inverted T-shaped central channel region is formed between adjacent source regions and drain region in the body region.

Fully depleted SOI device with tungsten damascene contacts and method of forming same

A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.

Self-aligned gate semiconductor

Aspects for more reliable particle removal from a semiconductor processing chamber following a chamber wet clean are described. With the present invention, an improved particle removal following wet cleans of semiconductor processing chambers occurs. The present invention creates a turbulent gas flow in a chamber in order to more thoroughly remove particles from the chamber, including those that the wet clean procedures cannot reach. In a straightforward and efficient manner, the turbulent gas flow is created by providing gas in both an upper and lower portion of the chamber substantially simultaneously, including the advantageous use of the backside helium available to chamber processing.

Reliable particle removal following a process chamber wet clean

A method of forming a T-shaped gate for a transistor, comprising: defining a base length of the gate by forming a gate stack on a substrate; defining a contact length by forming a layer of nitride on the gate stack; and defining gate height by selectively removing portions of the nitride layer. The method may include the further step of defining a contact height by depositing a conductive layer on said gate stack.

Method for fabricating T-shaped transistor gate

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San Jose, CA, United States of America

Allison Holbrook