The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2003
Filed:
Aug. 11, 2000
Applicant:
Inventors:
Zoran Krivokapic, Santa Clara, CA (US);
Allison Holbrook, San Jose, CA (US);
Sunny Cherian, San Jose, CA (US);
Kai Yang, San Jose, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ; H01L 3/10392 ; H01L 2/976 ; H01L 2/994 ;
U.S. Cl.
CPC ...
H01L 2/701 ; H01L 2/712 ; H01L 3/10392 ; H01L 2/976 ; H01L 2/994 ;
Abstract
A fully depleted field effect transistor formed in a silicon on insulator (SOI) substrate includes a body region formed in a silicon device layer over an isolation layer of the SOI substrate. A gate is positioned above the body region and includes a base gate region adjacent the body region and a wide top gate region formed of tungsten damascene and spaced apart from the body region. An inverted T-shaped central channel region is formed between adjacent source regions and drain region in the body region.