Tomohiko Kitajima

This inventor holds 37 USPTO granted patents and 15 published patent applications, primarily in 3D Memory Technology. Top assignee: Applied Materials, Inc.. Active years: 2006-2026.

USPTO Granted Patents = 37 (Patent Applications = 15)

% Patents Active = 86.5

Average Co-Inventor Count = 4.2

ph-index = 5

Forward Citations = 65(Granted Patents)

Location History:

Chiba, JP (2006)
Santa Clara, CA (US) (2015 - 2019)
San Jose, CA (US) (2016 - 2024)

Company Filing History:

37 out of 14,391

Applied Materials, Inc.

patents

Years Active: 2006-2026

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Areas of Expertise:

Silicon Nitride Deposition

Dynamic Random-Access Memory

3D NAND Structures

Charge Trap Layer

High Voltage MOSFET

Memory Cell Fabrication

Thermal Treatment

Chemical Mechanical Polishing

Vertical Drift Region

3D DRAM

Doped Hardmask

Eddy Current Measurement

37 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12713596 - POLY-SILICON BASED WORD LINE FOR 3D MEMORY (2026-08-18),

2. 12684758 - 3-D DRAM structures and methods of manufacture (2026-07-14),

3. 12592369 - Integrated method and tool for high quality selective silicon nitride deposition (2026-03-31),

4. 12581637 - Methods and structures for three-dimensional dynamic random-access memory (2026-03-17),

5. 12550317 - Direct word line contact and methods of manufacture for 3D memory (2026-02-10),

6. 12538490 - Confined charge trap layer (2026-01-27),

7. 12526971 - Reduced strain Si/SiGe heteroepitaxy stacks for 3D DRAM (2026-01-13),

8. 12482749 - L-type wordline connection structure for three-dimensional memory (2025-11-25),

9. 12477723 - Three dimensional memory device and method of fabrication (2025-11-18),

10. 12464716 - NAND cell structure with charge trap cut (2025-11-04),

11. 12444615 - Forming a doped hardmask (2025-10-14),

12. 12408370 - Structure and fabrication method of high voltage MOSFET with a vertical drift region (2025-09-02),

13. 12310014 - Selection gate separation for 3D NAND (2025-05-20),

14. 12148475 - Selection gate separation for 3D NAND (2024-11-19),

15. 12142475 - Sequential plasma and thermal treatment (2024-11-12),

Title: Top Inventor in San Jose

Introduction: Shan Liu is recognized as a leading inventor in San Jose, contributing significantly to various technological advancements.

Latest Patents: Shan Liu holds several patents that showcase innovative solutions in his field.

Career Highlights: Throughout his career, Liu has achieved numerous milestones that highlight his expertise and impact on technology.

Collaborations: He has collaborated with various organizations and professionals, enhancing the scope of his inventions.

Conclusion: Shan Liu continues to be a prominent figure in the world of innovation, inspiring future generations of inventors.