Applied Materials, Inc.

Tomohiko Kitajima

Chang Seok Kang

Gill Yong Lee

Sung-Kwan Kang

Mukund Srinivasan

Takehito Koshizawa

Jeffrey Drue David

Susmit Singha Roy

Jun Qian

Sanjay S Natarajan

Sidney P Huey

Garlen C Leung

Harry S Whitesell

Taketo Sekine

ChangSeok Kang

Nitin K Ingle

Abhijit Basu Mallick

Pramit Manna

Fred D Fishburn

Mihaela A Balseanu

Rui Cheng

Sony Varghese

Bo Qi

Rajesh Prasad

Shishi Jiang

Kyu-Ha Shim

Lequn Liu

Huiyuan Wang

Fredrick Fishburn

Ning Li

Brian J Brown

Thomas H Osterheld

Qian Fu

Kun Xu

Hui W Chen

Patricia M Liu

Jimin Zhang

Wen-Chiang Tu

Sarah Michelle Bobek

Joe Margetis

Zhihong Wang

Stephen Jew

Jim Kellogg Atkinson

David H Mai

Scott Falk

Deven Matthew Raj Mittal

Shuaidi Zhang

Clinton P Sakata

Gary Ka Ho Lam

Qi Gao

Gen Yasuhara

Balasubramanian Pranatharthiharan

Abdul Wahab Mohammed

Adaeze Osonkie

Shih-Haur Walters Shen

Kurt Decker-Lucke

Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

Reduced strain Si/SiGe heteroepitaxy stacks for 3D DRAM

A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

L-type wordline connection structure for three-dimensional memory

A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

Three dimensional memory device and method of fabrication

Described is a memory device including a plurality of memory cells formed around a memory hole extending through a memory stack on a substrate. Each of the plurality of memory cells comprises a discrete blocking oxide layer, a charge trap layer, and a tunnel oxide layer. The blocking oxide layer is discrete between each of the plurality of memory cells. The tunnel oxide layer is continuous between each of the plurality of memory cells, and the charge trap layer is discrete between each of the plurality of memory cells. The charge trap layer has a first thickness on a top portion and a second thickness on a center portion, the first thickness different than the second thickness.

NAND cell structure with charge trap cut

Methods for depositing a hardmask with ions implanted at different tilt angles are described herein. By performing ion implantation to dope an amorphous carbon hardmask at multiple tilt angles, an evenly distributed dopant profiled can be created. The implant tilt angle will determine a dopant profile that enhances the carbon hardmask hardness.

Forming a doped hardmask

Embodiments of the present disclosure include a transistor with a vertical drift region and methods for forming the transistor. The transistor may include a well region of a first conductivity type, a gate region disposed above the well region, and a drift region of a second conductivity type, different from the first conductivity type. The drift region may have a lateral portion disposed above a portion of the well region and laterally adjacent to a semiconductor channel in the well region. The drift region may also have a vertical portion extending vertically from the lateral portion of the drift region.

Structure and fabrication method of high voltage MOSFET with a vertical drift region

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating non-replacement word lines and replacement insulators. A filled slit extends through the memory stack, and there are at least two select gate for drain (SGD) isolation regions in the memory stack adjacent the filled slit. A select-gate-for-drain (SGD) cut is patterned into the top few pairs of alternating layers in the memory stacks. Through the cut opening, the sacrificial layer of the memory stacks is removed, and an insulator layer is used to fill the opening.

Selection gate separation for 3D NAND

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

Sequential plasma and thermal treatment

Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

Confined charge trap layer

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

3D DRAM structure with high mobility channel

Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.

3-d dram cell with mechanical stability

Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

3-D DRAM structures and methods of manufacture

Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

3D-NAND memory cell structure

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San Jose, CA, United States of America

Tomohiko Kitajima