The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2025

Filed:

Jul. 19, 2022
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Chang Seok Kang, Santa Clara, CA (US);

Fred Fishburn, Apotos, CA (US);

Tomohiko Kitajima, San Jose, CA (US);

Sung-Kwan Kang, San Jose, CA (US);

Sony Varghese, Manchester, MA (US);

Gill Yong Lee, San Jose, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H10B 12/50 (2023.02); H10B 12/09 (2023.02); H10B 12/30 (2023.02);
Abstract

A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.


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